Design Verification Engineer

Indiamid

OtherDesign Verification Engineer

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Quick Summary

Overview

We are at a pivotal moment in the semiconductor industry. Technology is evolving at an unprecedented pace, and Texas Instruments' MCU organization is right at the center of this transformation.

Key Responsibilities

Responsible for driving verification strategy, writing Test Plan, developing/modifying Test Bench. Working on SoC DV signoff using C and/or SV-UVM. Reuse of IP DV UVM components like agent, driver, monitor and score board at SoC.

Requirements Summary

3+ Years’ experience working on SoC/IP DV with a Bachelor or Master’s degree in EE/ECE/CS or related specializations Skills: Strong in digital design fundamentals, computer organization & architectures and bus protocols Excellent debugging and…

Technical Tools

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We are at a pivotal moment in the semiconductor industry. Technology is evolving at an unprecedented pace, and Texas Instruments' MCU organization is right at the center of this transformation.

Our current work is focused on developing solutions for high-growth markets — including AI-driven data centers and emerging domains such as humanoid systems. These areas are actively shaping the future of computing, automation, and intelligent systems, offering a rare opportunity to work on cutting-edge technologies with real-world, large-scale impact.

If you are passionate about solving complex technical challenges and want to contribute to innovations in these fast-growing segments, this is your moment. This role is not only technically rewarding — it is strategically significant.

Texas Instruments is seeking an experienced and driven DV engineer to shape the engineering strategy within our MCU organization.

Responsibilities

~1 min read

→Responsible for driving verification strategy, writing Test Plan, developing/modifying Test Bench.
→Working on SoC DV signoff using C and/or SV-UVM.
→Reuse of IP DV UVM components like agent, driver, monitor and score board at SoC.
→Define and meet all structural and functional coverage goals
→SoC verification (including low power verification) in RTL, GLS & AMS.
→Actively collaborate with IP/Architecture and RTL teams to enable meeting Verification goals for the SoC

Requirements

~1 min read

3+ Years’ experience working on SoC/IP DV with a Bachelor or Master’s degree in EE/ECE/CS or related specializations

Strong in digital design fundamentals, computer organization & architectures and bus protocols
Excellent debugging and problem solving skill
Experience in one or many of the following : UVM/System Verilog/C/C++/scripting, Simulation, Formal verification, or post Silicon validation
Thorough knowledge of standard protocols. Ex: AHB, APB, CAN, USB, I2C, SPI, UART, etc.
Exposure to AMS and/or Low Power Verification is a plus.
Effective communication skills to interact with all stakeholders.