SoC/IP Architect

Change the world. Love your job. 
In this position, you will be working on high-speed mixed-signal communication circuits using state-of-the art process technology, as well as be involved in the design of high performance digital circuits interfacing to leading edge analog circuitry as part of an overall system.

Your responsibilities will include RTL coding, simulation, synthesis, timing closure, verification, evaluation, debugging of high-speed communication chips both at the circuit level and behavioral level.

As a design engineer, you will prepare test methods and specifications, assist in preparation of application information, data sheets and demo boards. You will develop solutions to complex problems through assessment of various techniques and approaches. You will plan and organize work to ensure timely completion of many independent tasks with general instructions on routine tasks and with detailed instructions on new assignments.

This position involves routine communication with a highly talented team of analog and digital design engineers to solve problems and present information as well as active participation in work groups, providing ideas and collaborative teamwork.

Role: SoC/IP Architect 

Key Responsibilities

Architecture Definition and Design

• Define and document SoC architecture including system topology, IP selection, and integration strategy for complex mixed-signal MCUs
• Establish Performance, Power, and Area (PPA) targets and drive architectural decisions to meet these goals
• Design and optimize interconnect architectures including bus structures
• Perform hardware-software partitioning to optimize functionality across hardware accelerators and software implementations
• Create architectural models and simulations to validate design decisions early in the development cycle

IP Design and Integration

• Design, customize, or select IP blocks including processors, memory controllers, DSPs, accelerators, and peripherals
• Ensure IP blocks are reusable, configurable, and scalable across multiple product variants
• Select and integrate third-party and internal IP cores
• Define IP specifications and collaborate with IP design teams to ensure requirements are met

Optimization and Analysis

• Analyze and optimize data flow and memory hierarchy to eliminate bottlenecks and maximize system throughput
• Implement power management strategies and multi-domain power architecture
• Design security-aware architectures with hardware-based security features, secure boot, and isolation mechanisms
• Conduct performance analysis and trade-off studies to balance competing requirements
• Evaluate emerging technologies and methodologies for future product roadmaps

Cross-Functional Collaboration

• Work closely with RTL design, verification, physical design, and software teams to ensure architectural feasibility and successful implementation
• Support early software bring-up by providing architectural documentation and working models
• Collaborate with System Engineers and customers to understand application requirements and translate them into technical specifications
• Participate in design reviews and provide technical guidance to engineering teams
• Interface with validation teams to develop comprehensive test strategies and ensure design quality

Experience

• 8+ years of experience in SoC architecture, IP design, or chip development
• Proven track record of successful chip tape-outs and silicon bring-up
• Hands-on experience with SoC integration and managing complex multi-IP designs
• Experience defining and meeting PPA (Performance, Power, Area) targets for production chips