Sr Analog Physical Design Engineer | Kilby Labs

Senior Analog Physical Design Engineer position is available within Kilby Labs, the central R&D organization at TI.  The lab is chartered to develop novel and innovative technologies and strategies for new business opportunities, drive next generation differentiated technologies for existing businesses and recruit top technical talent for TI.  This role will require strong technical expertise, attention to detail, and the ability to deliver innovative solutions.

Responsibilities will include:

1.   Collaborating with our design teams, sometimes from multiple geographical locations, to understand the architecture and key requirements in the creation of test/production dies, and the managing of the circuit layouts from floor planning to fabrication. 

2.   Project lead and team leader, providing technical guidance, planning, timelines, and resource assignments.

3.   Conducting layout reviews and confirming all verifications and specifications have been met.

4.   Working with our design and packaging teams to develop custom lead-frames.

5.   Work closely with our ATD and PDK teams on new process and device development using Pcell Designer and other automated generation tools for various test vehicles.

6.   Analysis and closure of Electro Migration, Thermal gradients, and layout parasitics.

7.    Identifying ESD and latchup issues.

8.   Back annotation support.

9.   Mentor and guide contract layout engineers in India, review their work and provide feedback to meet quality and schedule expectations.

• Bachelor's degree in Electrical Engineering or related field.
• 8+ years of relevant experience

1.   Ability to establish strong relationships with key stakeholders critical to success, both internally and externally

2.   Strong verbal and written communication skills

3.   Demonstrated strong interpersonal, analytical and problem-solving skills

4.   Ability to take the initiative and drive for results

5.   Strong time management skills that enable on-time project delivery

6.   Familiar with multiple TI process nodes from our lbc, cmos, bicmos, and gan technologies.

7.   Ability to collaborate effectively with our design, pdk and packaging teams to help drive new innovations and troubleshoot problems.

8.   Eager to learn new tools and help in their implementation within TI.

9.   Ability to quickly ramp on new systems and processes.

10.  Working knowledge of database management, caps execution and maintenance, and JUMP updates.

11.   Expert in layout techniques, tools, and methodologies used for power, rf, and sensor layouts. 

12.  Proficient problem solving, documentation and organizational skills.

13.  Familiar with Cadence Allegro, TOTEM, and Pcell Designer a plus, but not required.