Senior DFT Engineer

We are looking for a highly motivated Senior DFT Engineer to join our Silicon Engineering team. In this role, you will be responsible for architecting, implementing, and validating Design-for-Test (DFT) solutions for complex SoCs. You will work closely with RTL, Physical Design, ATPG, Verification, and Product Engineering teams to ensure high manufacturing test coverage, quality, and silicon reliability.

• →Develop and implement DFT architecture for complex SoCs, including Scan, MBIST, Boundary Scan (JTAG), and Compression techniques.
• →Integrate DFT logic into RTL while ensuring minimal impact on design performance, power, and area.
• →Execute scan insertion, DFT synthesis, and DFT rule checks (DRC).
• →Generate and validate ATPG patterns for stuck-at, transition, path delay, and bridge fault models.
• →Analyze test coverage reports and drive improvements to achieve production-quality coverage.
• →Perform gate-level simulations and debug DFT-related issues throughout the design cycle.
• →Collaborate with RTL, Physical Design, Verification, and Product Engineering teams during implementation and silicon bring-up.
• →Support silicon validation, failure analysis, yield improvement, and manufacturing test optimization.
• →Develop and maintain DFT methodologies, automation scripts, and best practices.
• →Participate in design reviews and provide technical guidance on DFT implementation.

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
• 3–6 years of hands-on experience in Design for Test (DFT) for ASIC/SoC development.
• Strong understanding of digital design fundamentals and ASIC design flow.
• Experience implementing Scan, MBIST, JTAG/IEEE 1149.1, Compression, and ATPG methodologies.
• Hands-on experience with DFT insertion, ATPG generation, and coverage analysis.
• Strong debugging skills and understanding of gate-level simulations.
• Good knowledge of timing, synthesis, and low-power design concepts.
• Excellent analytical, problem-solving, and communication skills.

• Experience with industry-standard EDA tools such as:
  • Siemens Tessent
  • Synopsys TestMAX / DFT Compiler
  • Cadence Modus
• Knowledge of ATPG fault models including Stuck-at, Transition, Path Delay, Cell-aware, and Bridge faults.
• Familiarity with IJTAG (IEEE 1687), LBIST, OCC, and Memory Repair concepts.
• Experience with scripting languages such as Tcl, Perl, Python, or Shell.
• Understanding of UPF/CPF and low-power DFT implementation.
• Exposure to advanced process nodes (16nm, 7nm, 5nm, or below) is an advantage.

• Experience working on large-scale SoC designs with multiple clock domains.
• Exposure to silicon bring-up, production test, and yield enhancement.
• Ability to work effectively in cross-functional and globally distributed teams.
• Experience mentoring junior engineers is a plus.

• Strong ownership and accountability.
• Excellent collaboration and communication skills.
• Ability to thrive in a fast-paced, innovative engineering environment.
• Passion for solving complex technical challenges and delivering high-quality silicon.