Soc Design Verification Director

We are seeking a seasoned Director of SoC Design Verification with 20+ years of experience to lead verification for our next-generation System-on-Chip products. This is a hands-on leadership role where you will define the SoC-level verification strategy, oversee execution across multiple IPs and subsystems, and ensure first-pass silicon success for complex designs in compute, networking, and storage domains.

• →Own and drive the end-to-end SoC verification methodology, ensuring seamless integration of IP-level verification into system-level environments.
• →Lead, mentor, and grow a diverse team of engineers, fostering technical excellence, innovation, and collaboration.
• →Guide verification of complex SoC subsystems including HSIO, peripherals, interconnects, memory controllers, coherency fabrics, and system-level protocols.
• →Champion advanced methodologies (UVM, formal verification, emulation, AI-augmented flows) to accelerate coverage closure and improve efficiency.
• →Collaborate closely with RTL design, architecture, firmware, and validation teams to debug, refine, and optimize SoC-level verification processes.
• →Represent verification in executive reviews, customer engagements, and industry forums.
• →Shape workforce transformation by building hybrid skill sets and preparing the team for AI-driven verification challenges.

• Bachelor’s degree in Electrical or Computer Engineering (Master’s preferred).
• 20+ years of experience in design verification, with a proven track record of leading teams and delivering complex SoC/silicon products.
• Deep expertise in SoC-level verification, including interconnect fabrics, coherency protocols, HSIO, and peripheral subsystems.
• Strong background in UVM-based test plan development, assertions, coverage analysis, and abstraction layer design.
• Demonstrated ability to manage priorities, engage with stakeholders, and drive organizational success.

• Hands-on expertise with SoC-level verification environments, including integration of multiple IPs, HSIO, and peripherals.
• Deep experience in UVM-based test plan development, sequence generation, and coverage analysis.
• Strong background in writing assertions, cover properties, and analyzing coverage data at both IP and SoC levels.
• Experience in developing scalable verification infrastructures to simplify and accelerate SoC-level deployments.

• Expertise in verifying complex SoC subsystems such as NoC-based interconnects, coherency fabrics, HSIO, and memory hierarchies.
• Experience with buffering, queuing, QoS, and system-level performance analysis.
• Familiarity with emulation, FPGA prototyping, and hybrid verification flows.
• Knowledge of AI-driven verification methodologies and workforce transformation strategies.
• Experience with AI/ML accelerators, networking, automotive, data center, or high-performance computing SoCs.
• Familiarity with low-power verification methodologies and power-aware verification.
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