Senior/Staff Mid-End Engineer (3D/Process Integration)

Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud.

Bitdeer is committed to providing comprehensive Bitcoin mining solutions for its customers. Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles complex processes involved in computing across the value chain. This includes equipment procurement, transport logistics, datacenter design and construction, equipment management, and network and facility operations. Bitdeer also offers advanced cloud capabilities to customers with a high demand for artificial intelligence.

Headquartered in Singapore, Bitdeer operates globally with a diversified 3 GW energy portfolio, and deploys Bitcoin mining and HPC datacenters in the United States, Bhutan, Norway, Canada, Malaysia, and Ethiopia.

• →Own the WoW stack definition and the TSV / hybrid-bond (HB) interface between the logic die and the stacked DRAM — partition, bond-pad pitch/array, keep-outs, and alignment budgets — co-defined with the foundry and the memory partner.
• →Drive the 3D-aware floorplan inputs: bump/TSV/HB maps, micro-bump and ballmap planning, and die-to-die interface placement, in partnership with Physical Design.
• →Define and close DFM and 3D design rules; run design-rule and process-assumption reviews against the foundry's 3DFabric kit and the DRAM partner's collateral.
• →Coordinate thermal and thermal-mechanical (stress / warpage) analysis for DRAM-on-logic, and feed mitigations back into floorplan, power delivery, and stack choices.
• →Drive 3D signoff: thermal, SI/PI across the die-to-die interface, and known-good-stack assumptions — clean before tapeout.
• →Work with DFT on the 3D test strategy (stacked-die test access, IEEE 1838 / known-good-die & known-good-stack) so the integration is testable.
• →Manage package / substrate co-design handoff to the OSAT (outsourced): stackup, escape, assembly flow, and yield/reliability considerations.
• →Track foundry and memory-partner deliverables and milestones, surface integration risks early, and keep the stack plan aligned with the schedule.

• →A culture that values authenticity and diversity of thoughts and backgrounds;
• →An inclusive and respectable environment with open workspaces and exciting start-up spirit;
• →Fast-growing company with the chance to network with industrial pioneers and enthusiasts;
• →Ability to contribute directly and make an impact on the future of the digital asset industry;
• →Involvement in new projects, developing processes/systems;
• →Personal accountability, autonomy, fast growth, and learning opportunities;
• →Attractive welfare benefits and developmental opportunities such as training and mentoring.

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Bitdeer is committed to providing equal employment opportunities in accordance with country, state, and local laws. Bitdeer does not discriminate against employees or applicants based on conditions such as race, colour, gender identity and/or expression, sexual orientation, marital and/or parental status, religion, political opinion, nationality, ethnic background or social origin, social status, disability, age, indigenous status, and union.

• BS/MS/PhD in EE, Materials, Mechanical Engineering, or a related field.
• 5+ years in 3DIC / advanced-packaging / process integration, with at least one product taken to tapeout and through assembly.
• Direct, hands-on experience with TSV and hybrid bonding and a 3D stacking flow (wafer-on-wafer, chip-on-wafer, or SoIC/CoWoS-class).
• Working knowledge of TSMC 3DFabric (SoIC / CoWoS / InFO) or an equivalent foundry 3D ecosystem, including the associated design kits and rule decks.
• Solid grasp of thermal / thermal-mechanical behavior in stacked die and of SI/PI at the die-to-die interface.
• Comfortable owning cross-organization interfaces - foundry, memory IP partner, and OSAT - and translating their constraints into actionable design inputs.

• Experience with DRAM-on-logic stacks, HBM-class memory integration, or high-bandwidth memory interfaces.
• Background on AI / HPC accelerators or other high-power, high-bandwidth SoCs.
• Familiarity with thermal/mechanical tools (e.g., Ansys) and 3D physical/signoff flows (Synopsys / Cadence).
• Exposure to stacked-die test and yield debug.
• Experience standing up a 3D-integration methodology on a small team - comfortable being the first/only specialist in the room.

• You own a genuinely hard, defining problem on the chip - not a slice of someone else's flow.
• Direct line to the foundry and memory partner; your decisions set the stack.
• Early-team seniority with room to shape the 3D methodology and grow the function.