Principal Design Verification Engineer

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• 10+ years of Design Verification experience (or MS/PhD with 5+ years).

• Strong experience with SystemVerilog and UVM.

• Experience with SoC/ASIC verification and successful tape-outs.

• Expertise in constrained-random and coverage-driven verification.

• Python or Perl scripting experience.

• Experience with EDA verification tools.

• Strong Linux, C++, and Object-Oriented Programming skills.

• ARM Assembly experience preferred.

Equal Employment Opportunity (EEO) Statement

Bright Vision Technologies (BV Teck) is committed to equal employment opportunity (EEO) for all employees and applicants without regard to race, color, religion, sex, sexual orientation, gender identity or expression, national origin, age, genetic information, disability, veteran status, or any other protected status as defined by applicable federal, state, or local laws. This commitment extends to all aspects of employment, including recruitment, hiring, training, compensation, promotion, transfer, leaves of absence, termination, layoffs, and recall.

BV Teck expressly prohibits any form of workplace harassment or discrimination. Any improper interference with employees' ability to perform their job duties may result in disciplinary action up to and including termination of employment.