Design Verification (DV) Engineer

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OtherDesign Verification Engineer
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Quick Summary

Key Responsibilities

We are seeking a IP DV engineer with significant hands-on experience in pre-silicon Design verification, verification methodologies and UVM/OVM.

Requirements Summary

Good understanding of verification process from test plan to coverage completion Strong communication and Analytical skills Understanding of HDL (Verilog,

Technical Tools
OtherDesign Verification Engineer
There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Responsibilities

~2 min read

Responsibilities & Skills:

We are seeking a IP DV engineer with significant hands-on experience in pre-silicon Design verification, verification methodologies and UVM/OVM.

  • Develop and Review Test Plan based on design specification
  • Develop constrained-Random verification environment for complex DUT
  • Implement coverage metrics using cover point and assertion
  • Create and debug tests for DUT
  • Resolve bugs with remote designers

Requirements:

  • Good understanding of verification process from test plan to coverage completion
  • Strong communication and Analytical skills
  • Understanding of HDL (Verilog, SystemVerilog)
  • Experience with designing with FPGA is a plus
  • Programming skills (e.g.: C/C++, Perl, TCL or Python).
  • Experience in following technology areas are an added advantage : High speed SERDES protocols (PCIe, Ethernet, CPRI or JESD204B/C, USB), Memory (DRAM, SRAM, Flash, DMA), Interconnect (AMBA AXI, AHB, APB), Peripherals (SPI, I2C or I3C)

Education and General:

  • BS/MS/PhD in Electronics or Computer Engineering minimum of 2 years of SystemVerilog/UVM
  • Independent and self-motivated, capable of executing under dynamic environment and uncertainties

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry.  Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.

Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.  Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win.  For more information about how our FPGA, CPLD and programmable power management  devices help our customers unlock their innovation, visit www.latticesemi.com.  You can also follow us via Twitter, Facebook, or RSS. At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.  Applications are welcome from all qualified candidates.

Lattice

Feel the energy.

Location & Eligibility

Where is the job
Location terms not specified
Who can apply
Open to applicants worldwide

Listing Details

Posted
May 12, 2026
First seen
June 13, 2026
Last seen
June 13, 2026

Posting Health

Days active
0
Repost count
0
Trust Level
11%
Scored at
June 13, 2026

Signal breakdown

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careers-latticesemiDesign Verification (DV) Engineer