Staff EDA Engineer – RTL Front End Tools & Methodologies

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Pune, India – Non‑negotiable

Hybrid with mandatory 4 days per week working from the Pune office

We are seeking a Staff EDA Engineer with strong expertise in RTL front‑end methodologies, power analysis, and simulation tool support. This role requires technical ownership and leadership in enabling scalable, high‑quality RTL flows, driving low‑power initiatives, building automation, and adopting Generative‑AI capabilities within EDA tools.

The ideal candidate will work closely with design, verification, CAD, and EDA vendor teams, contributing both to day‑to‑day project enablement and to long‑term front‑end EDA strategy. This is a hands‑on, high‑impact role requiring regular collaboration from the Pune site.

• →Act as technical owner for RTL front‑end EDA methodologies, including simulation, power analysis, and constraint validation.
• →Lead and drive RTL low‑power initiatives, defining and enabling power‑aware RTL methodologies across projects.
• →Enable and support RTL power analysis flows using PowerArtist and Joules, including methodology definition, debug, optimization, and best‑practice guidance.
• →Provide expert‑level support for RTL simulation and debug using QuestaSim, Synopsys VCS, and Cadence Xcelium.
• →Own SDC constraint understanding, validation, and verification, ensuring correctness and consistency with downstream flows.
• →Drive adoption of Generative‑AI enablement in EDA workflows, leveraging AI/ML features available in EDA tools, intelligent log analysis, and productivity automation.
• →Architect, develop, and maintain automation frameworks using Python (and Tcl/Shell as needed) for flow execution, regression, analysis, and reporting.
• →Collaborate closely with design and verification teams through regular in‑office interactions to resolve complex RTL, power, simulation, and tool‑related issues.
• →Serve as the primary interface with EDA vendors, leading tool issue debug, enhancement requests, version qualification, and roadmap alignment.
• →Develop and maintain methodology documentation, user guidelines, and training material for front‑end users.
• →Mentor junior engineers and contribute to raising the overall technical bar of the EDA organization.

• 9–11 years of experience in EDA tools, RTL front‑end methodologies, or CAD engineering roles.
• 5+ years of strong hands‑on expertise in RTL power analysis using PowerArtist and Joules.
• Proven experience driving low‑power initiatives at RTL level, including:
  • Defining and enabling power‑aware RTL methodologies
  • Supporting power optimization, analysis, and reduction strategies
  • Partnering with design teams to improve power efficiency early in the design cycle
• Solid understanding of SDC constraints, constraint checks, and front‑end timing concepts.
• Advanced automation skills, with strong proficiency in Python programming for EDA flow development, analysis, and reporting.
• Strong problem‑solving skills with the ability to debug complex tool, power, and methodology issues.

• Experience applying Generative‑AI / ML techniques to EDA workflows (log analysis, flow intelligence, automation).
• Exposure to RTL quality checks such as Lint, CDC/RDC, or power‑intent verification.
• Exposure to supporting RTL flows using QuestaSim, VCS, and Xcelium.
• Understanding of how RTL decisions impact synthesis, STA, and physical design.
• Strong communication skills and experience working with global, cross‑functional teams.