ASIC Top Level Verification- HW Emulation

## About this opportunity Join our new ASIC top level verification team. We specialize in the top-level verification of cutting-edge ASICs that power complex high-performance systems. Our designs are either monolithic ASICs or integrated multi-chip-modules holding several hundreds of processor cores, DSPs as well as ARM cores, tailored hardware accelerator IPs and many high-speed interfaces, including Ethernet, CPRI, and PCIe. As an ASIC Top-Level Verification Engineer, you'll be part of a team tackling some of the most challenging verification tasks in the industry, ensuring that our ASICs meet our high standards for performance, functionality, and security. You will play an important role in the team developing environments and/or tests run in SystemC/TLM simulation, RTL environments, hardware emulation, and eventually on Silicon. ## What you will do * Bringing our ASIC designs into a Hardware emulator. * Developing transactors to enable hybrid environments or usage of testbench run in simulation * Together with TLM developers, develop hybrid environments where the ASIC is split so that one part is running emulation and the other part in TLM/SystemC. * Update and maintain existing emulator platforms running ASIC under development as well as legacy ASICs * Manage regressions running in emulation and help out solving testcase issues and debug failing tests. ## You will bring Preferably experience in * Experience of HW Emulation using Siemens Veloce and/or Cadence Palladium. * Experience in writing transactors. * TLM / Emulation hybrid environments * How to enable UPF support * RTL debugging with experience using Waveform debugging tools from one of the three largest EDA vendors * Development of C SW targeting embedded system, using SW debuggers for debugging. * Updating testbenches, like adding VIPs * It is a plus with basic understanding of UPF and even better with experience from running low power simulations using UPF