Emulation Engineer

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

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• Bring up a new subsystem partition on HAPS and get firmware booting on it end to end.

• Build a self-service flow that lets software users load and run their own images without prototyping support in the loop.

• Instrument deep trace capture across partition boundaries and build the tooling that surfaces it usefully.

• Create configurable chip-to-chip and off-chip interface models using prototyping-efficient primitives.

• Close timing on a partition that doesn't want to close, and document how you did it so the next person doesn't have to rediscover it.
  

• Hands-on FPGA prototyping experience — HAPS, Protium, proFPGA, S2C, or similar — covering partitioning, synthesis, timing closure, bring-up, and debug.

• Strong SystemVerilog and Verilog, with a working understanding of what synthesizes well for FPGA and what doesn't.

• Solid C/C++ and Linux system development.

• Scripting fluency for automation — Python, TCL, shell.

• Comfort debugging failures you didn't cause, in code you didn't write, for users who need an answer today.

• Experience with ProtoCompiler, Vivado, or Synopsys prototyping flows.

• Firmware, driver, or bootloader bring-up experience on pre-silicon platforms.

• Experience with emulation platforms (ZeBu, Palladium, Veloce) alongside prototyping — we run both, and the collateral is shared.

• UVM verification environments, DFT, and testbench modeling.

• Waveform debug tooling: Verdi, SimVision.

• Cluster and job scheduling experience (SLURM), CI systems.
  

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.