Formal Verification - DV

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

We are seeking a Formal Verification Engineer to join our ASIC Design Verification team. You will drive formal verification across the custom IP, interface IP, and SoC subsystems that power our ASICs, including compute arrays, DMA engines, NoCs, memory systems, PCIe, Ethernet, CPU subsystems, low-power peripherals, and vendor IP wrappers. You will work closely with architects, RTL designers, DV engineers, emulation teams, and software/firmware teams to prove design correctness, expose deep corner-case bugs, and improve verification closure across the full chip.

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  Define and drive formal verification strategy across the ASIC DV team for complex IP blocks, interface subsystems, and SoC integration logic.

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  Develop formal verification plans covering functional correctness, connectivity, ordering, reset behavior, configuration legality, and deadlock/livelock freedom.

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  Build reusable formal environments using SystemVerilog Assertions, assumptions, constraints, checkers, cut-points, abstraction models, and reference models.

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  Drive proof convergence using abstractions, cut-points, assume-guarantee reasoning, cover properties, bounded-proof analysis, and coverage metrics to establish formal sign-off confidence.

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  Work with architects and RTL designers to translate design intent and specifications into high-value formal properties and closure criteria.

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  Partner with UVM DV, emulation, software, and firmware teams to align formal verification with simulation, coverage, regressions, and bring-up.

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  Debug complex RTL, protocol, datapath, connectivity, and integration bugs using formal counterexamples, waveforms, and design analysis.

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  Contribute to formal sign-off methodology, regression automation, reporting, and design-for-formal best practices.

• 5+ years of design verification experience, including significant hands-on formal verification experience on complex digital designs or shipping silicon.

• Strong proficiency with SystemVerilog, SystemVerilog Assertions, and formal verification methodology.

• Experience with commercial formal tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal.

• Strong understanding of digital design, computer architecture, datapaths, interconnects, memory systems, and standard SoC interfaces.

• Ability to model complex design behavior using assumptions, abstractions, constraints, cut-points, checkers, and reference models.

• Strong debugging skills across RTL, specifications, formal counterexamples, simulation waveforms, and verification reports.

• Experience collaborating across architecture, RTL design, UVM DV, emulation, software, firmware, and vendor teams.

• You thrive in a fast-paced startup environment and can take ownership of ambiguous, high-impact verification problems.

• Formal verification of systolic arrays, DMA engines, NoCs, memory subsystems, arithmetic datapaths, PCIe, Ethernet, AXI/AMBA, CPU interfaces, or low-power controllers.

• Protocol compliance checking, connectivity checking, register verification, datapath validation, reset verification, or deadlock/livelock analysis.

• Vendor IP integration, encrypted or black-box IP verification, VIP configuration, and contract-based verification around subsystem boundaries.

• Sequential LEC, floating-point or integer arithmetic proofs, cache coherency checks, interrupt handling, or memory-mapped IO verification.

• Scripting in Python, TCL, Perl, or similar for automation, regression management, debug, and dashboarding.

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.