Senior Engineer - QPU Testing

IonQ, Inc. [NYSE: IONQ] is the world’s leading quantum platform and merchant supplier - delivering integrated quantum solutions across computing, networking, sensing, and security. IonQ’s newest generation of quantum computers, the IonQ Tempo, is the latest in a line of cutting-edge systems that have been helping customers and partners including Amazon Web Services, and AstraZeneca achieve 20x performance results and accelerate innovation in drug discovery, materials science, financial modeling, logistics, cybersecurity, and defense. In 2025, the company achieved 99.99% two-qubit gate fidelity, setting a world record in quantum computing performance.

Headquartered in College Park, Maryland, IonQ has operations in California, Colorado, Massachusetts, Tennessee, Washington, Italy, South Korea, Sweden, Switzerland, Canada, and the United Kingdom. Our quantum computing services are available through all major cloud providers, while we also meet the needs of networking and sensing customers across land, sea, air, and space. IonQ is making quantum platforms more accessible and impactful than ever before.  

The mission of the QPU Testing team is to improve quantum computer performance through validation of QPU (quantum processing unit) designs and verification of individual QPUs produced by the manufacturing team. We own the creation and execution of test plans that we develop with stakeholders across the Quantum Computing organization. We are looking for a Senior Engineer to join the QPU Testing team at the boundary between QPU Testing, QPU Packaging, and QPU Manufacturing. In this role, you will ensure our testing accurately captures device quality and performance characteristics that are important to both the fabrication and packaging teams. You will also serve as a trusted internal authority on package-level and die-level test validity, rigor, and interpretation.

You will help to translate fabrication and packaging risk areas into concrete, executable test plans — including die-level electrical screening, package-level qualification, and non-ion device characterization — then communicate results, interpretation, and actionable feedback to stakeholders. This role is central to maintaining a trusted testing roadmap and ensuring tight feedback loops between manufacturing, packaging, and system integration.

Responsibilities:

• Drive creation and evolution of die-level and package-level test plans, procedures, and acceptance criteria, aligned to fabrication and packaging priorities.
• Translate manufacturing requirements and packaging risk areas into practical, executable test coverage and readiness standards for QPU testing platforms.
• Provide technical triage for complex, ambiguous device and packaging issues, defining next diagnostics and escalation paths.
• Execute and validate testing campaigns hands-on, including operation of probe stations, PCB-based test fixtures, and package-level electrical characterization setups.
• Design and build test hardware (PCBs, breakout boards, test fixtures) to support expanding QPU package formats.
• Communicate results and recommendations clearly across packaging, fabrication, and cross-functional stakeholders.

You’d be a good fit with: 

• MS/PhD in electrical engineering, applied physics, materials science, or a closely related field, and 4+ years of relevant industry experience.
• Hands-on experience with die-level or package-level electrical characterization (probe station operation, IV curves, continuity/opens/shorts testing).
• Demonstrated ability to independently define next steps, prioritize work, and execute with minimal supervision.
• Strong electronics fundamentals (PCB design and bring-up, signal integrity, connector and cabling systems) and comfort debugging complex hardware setups.
• Python scripting for test automation, data acquisition, and analysis workflows.

You’d be a great fit with:

• Experience working at the boundary of semiconductor fabrication, advanced packaging (wire bonding, flip-chip, or similar), and system integration.
• Track record owning end-to-end test strategy (metrics to procedures to execution to reporting) for complex hardware platforms.
• Familiarity with cryogenic or vacuum-compatible electronics and packaging constraints.
• Experience working in highly collaborative, cross-disciplinary teams and influencing test priorities across org boundaries.
• Background in MEMS, photonics, or novel semiconductor device characterization.

If you are interested in being a part of our team and mission, we encourage you to apply!