Power Integrity Senior Engineer

## Company: Qualcomm India Private Limited ## Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Job Description (PDN – Power Integrity Engineer): * Ability to extrapolate and predict traditional electrical behavior using various AI/ML techniques. * Strong in analog and digital design and circuits * Extraction of PDN parameters using industry standard tools. * Good understanding of package and PCB. * Work with package and board design teams to enable analysis and closure of PDN rails. * Design power delivery network for die, package and board. Define bump/BGA patterns for on-die power grid and decoupling capacitance analysis. * Perform PDN design, simulation, analysis, and debug. * Derive PDN design budgets like IR Drops, droops, PMIC requirements. * Conduct power integrity analysis for high performance IPs, and provide feedback for Low Power Chip and System Architecture. * Work with system designers, design verification and physical design teams to define, implement, and verify power delivery. * Good understanding of power, timing, IR drop and issues seen in lower tech nodes. * Participate in development of PDN methodology formulation. * Lab measurements of PDN in frequency and time domain. * Good communication skills and ability to work with cross functional teams. Requirements: * Masters/Phd/Postdoc Candidates with 4-7 years of industry experience in power delivery network design and signal integrity analysis. * Expertise in signal and power integrity with preferred experience in on-die power grid design, decoupling capacitor analysis, and coupling analysis. * Expertise in cost-effective Power Distribution network design for high density/high performance chips. * Measurements skills: VNA, spectrum analyzer, oscilloscope. * Looking for candidates holding Masters/PhD in ECE with 4-7 years experience in signal and power integrity domain with understanding of power delivery networks and system design for high density/high performance chips. Additional Toolset Experience: * Conversant in languages (python/tcl/C), with understanding of software algorithms and data structures. * Cadence APD, Voltus, PowerSi, Ansys HFSS, Q3D, SiWave, HSpice, ADS and Matlab. Applicants: Qualcomm is an equal opportunity employer. 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