Design Engineering Intern
United States·San JoseentryQuick Summary
Perform design database management; proper check-in’s of golden files, reverting unused changes, merge different files. Should be able to code RTL logic with Verfilog syntax.
BS/MS degree (completed or in progress) in Electrical Engineering, Electronics, Computer Science, or a related field. Must have proficiency in Verilog, SystemVerilog programming language.
We are seeking a highly motivated and detail-oriented intern to join our team to contribute to ongoing ASIC project.
Responsibilities
~1 min read- →Have a mindset on problem solving.
- →Understand ASIC/FPGA workflow from concept to real silicon
- →Scripting language skills such as Python, Perl, Tcl, etc.
What We Offer
~1 min read
Location & Eligibility
Listing Details
- Posted
- July 15, 2026
- First seen
- July 16, 2026
- Last seen
- July 16, 2026
Posting Health
- Days active
- 0
- Repost count
- 0
- Trust Level
- 71%
- Scored at
- July 16, 2026
Signal breakdown
Please let SK hynix memory solutions America Inc. know you found this job on Jobera.
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