ASIC Design Intern

You will join the System on Chip (SoC) Design Team at SK hynix memory solutions America, a group dedicated to delivering best-in-class controllers for high-performance SSDs. This team spans the full design cycle—from micro-architecture and RTL design to timing closure and tapeout readiness—enabling next-generation enterprise and AI data center storage solutions.

• →RTL design (Verilog/SystemVerilog) for IP based on existing module or new specifications.
• →Collaborate, create clear documentation and communication with Design Verification, Silicon Validation, and Firmware teams to ensure design quality.

• Education: Currently enrolled in BS/MS/PhD program in Electrical Engineering, Computer Engineering, or related field.
• Proficiency in logic design and micro-architecture; RTL coding in Verilog and/or SystemVerilog language.

• Advanced Education: Master’s or PhD in Electrical Engineering with working experiences.
• Experience or coursework in digital logic design, verification methodologies, and protocols (AMBA, PCIe, NAND, DDR).
• Scripting skills (Python, Perl, TCL) and Linux command-line experiences.
• Strong problem-solving and communication skills.
• Proficiency in AI tool to generate synthesizable and functional RTL code.