Sr./Staff/Sr. Staff ASIC Design Engineer

We are seeking a highly skilled and experienced ASIC Design Engineer to join our ASIC design team. The role spans from RTL design through timing closure and tapeout readiness, with increasing responsibility based on seniority level (Sr., Staff, Sr. Staff). You will own critical modules or subsystems, drive design methodology improvements, and mentor junior engineers. Ideal candidates have 3+ years of industrial ASIC experience and a proven track record of successful tapeouts.

• Design, simulate, and verify RTL modules using Verilog/SystemVerilog.
• Participate in design reviews, linting, CDC, and power analysis.
• Debug and resolve functional/timing issues across design stages.
• Collaborate with verification, DFT, physical design, and architecture teams.
• Contribute to design automation (Tcl/Python/Perl scripts) and methodology enhancements.

• Own complex IP blocks or subsystems end-to-end (from spec to tapeout).
• Lead design reviews, drive design signoff, and ensure quality across the team.
• Mentor junior engineers and set best practices for RTL coding, linting, CDC, etc.
• Interface with cross-functional teams (verification, physical design, packaging, test) to resolve critical issues.
• Contribute to architecture discussions and micro-architecture trade-offs.

• 3+ years of industrial experience in ASIC design.
• Strong proficiency in RTL design using Verilog/SystemVerilog; familiarity with UVM is a plus.
• Familiarity with standard interfaces (AXI, AHB, APB, SMBus, UART, etc.).
• Proficiency in Tcl/Python/Perl/Shell for automation and flow customization.
• Strong communication, problem-solving, and teamwork skills.

• Successful tapeout(s) in advanced nodes.
• Experience with ARM/RISC-V-based SoCs or custom accelerators.
• Experience with UVM-based testbenches.
• Knowledge of UPF/CPF, power gating, clock gating.
• Understanding of floorplanning, placement, routing impact on timing.
• For Staff/Sr. Staff roles — demonstrated ability to lead design efforts or mentor