Tenstorrent~5mo ago

Sr. Engineer, SoC Design Verification

United States·Boston,Toronto,Santa Claralead

OtherEngineer

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Quick Summary

Overview

Requirements Summary

Deeply curious about silicon debug/test infrastructure and its verification. Expert in UVM and verification of DFT/DFD features, scan, and on-chip trace logic.

Technical Tools

networking

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is seeking a Senior SoC Design Verification Engineer who will focus on pre-silicon verification of PCIe logic in advanced AI SoCs, driving coverage of connectivity, compliance, interoperability, and bring-up features critical to silicon success.

This role is hybrid, based out of Boston, MA; Toronto, ON; or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Deeply curious about PCIe architecture, link behavior, and subsystem verification.
Expert in UVM and verification of PCIe controller, PHY-facing logic, LTSSM, and protocol flows.
Comfortable working with PCIe Gen4/Gen5 features, compliance concepts, and advanced verification automation.
Proactive, detail-oriented, and thrives in cross-functional technical discussions.
Ideally familiar with tools similar to CocoTB.

Requirements

~1 min read

Develop and own verification environments for PCIe logic across AI chiplets and SoCs.
Write, refine, and execute test scenarios for link training, enumeration, power management, error handling, and data movement features.
Analyze coverage gaps, debug failures, and collaborate closely with architecture, RTL, and system teams.
Automate flows for PCIe protocol testing, interoperability validation, and integrate AI productivity tools.

Responsibilities

~2 min read

→In-depth PCIe verification using cutting-edge workflows, tooling, and scripting.
→Integration of pre-silicon PCIe verification with silicon bring-up and platform validation strategies.
→How AI-driven automation reshapes modern DV workflows.
→Exposure to high-performance, system-level connectivity verification in advanced SoC designs.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.