Analog Layout Engineer - AI/ML methodology

Are you a layout engineer who thinks in polygons and code? Texas Instruments is looking for an Analog Layout Engineer to join a first-of-its-kind team where classical analog IC layout meets artificial intelligence. This is a rare opportunity to be part of a small, high-impact group that is actively shaping how analog products are built at one of the world's leading semiconductor companies.

As an Analog Layout Engineer, you will create physical layouts for integrated circuit designs that help bring new TI products to life and make our customers' visions a reality. You will implement, optimize, and verify analog IC layouts across a wide range of end equipment, including audio, imaging, high-speed, interface, clocking, medical, high volume linear, automotive, storage, power supply, battery management, and linear power applications.

You will work on state-of-the-art wafer processes, learning from and collaborating with industry experts in a unique interdisciplinary team with a fast-paced, startup-like environment. Your day-to-day work will include creating custom layouts, performing DRC/LVS verification, implementing matching and symmetry techniques, managing parasitic extraction, and collaborating closely with design engineers on post-layout simulations.

Beyond traditional analog layout, you will apply AI/ML-enabled tools and flows to accelerate layout development, optimize device matching, predict parasitic effects, and automate repetitive tasks. You will own and drive the adoption of these tools and flows across TI product teams, and you will have the creative freedom to develop novel ideas that can be patented and published. You will also gain exposure to Design Verification and Analog Design through formal learning, projects, and on-the-job experiences that will broaden your knowledge and accelerate your growth at TI.

Bring your layout expertise and AI/ML skills to this role and make an impact across the company!

• Bachelor's in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related field 
•  2 to 5 years experience
• Cumulative 3.0/4.0 GPA or higher

• Strong fundamentals in analog layout concepts with relevant coursework and layout projects
• Course project or internship experience in the layout of one or more analog IPs, such as band-gap reference, ADC, DAC, amplifier, oscillator, comparator, IO cells, and power-management blocks like LDO and DCDC
• Understanding of device matching, symmetry, guard rings, shielding, and parasitic management techniques
• Familiarity with DRC, LVS, parasitic extraction, and EM/IR analysis
• Working knowledge of Cadence Virtuoso Layout Suite and verification tools
• Foundational proficiency in Python and one or more packages such as Pandas, PyTorch, TensorFlow, scikit-learn, and Matplotlib
• Foundational knowledge of machine learning concepts such as Neural Networks, Graphs, Clustering and Regression techniques, and Decision Trees
• Strong verbal and written communication skills
• Demonstrated analytical and problem-solving skills, especially in new domains
• Ability to work in teams across time zones and collaborate effectively with people in different functions
• Ability to take initiative and drive for results in a timely manner