Design Verification

ACG_3441_JOB Our client is a technology company that is looking for a qualified candidate to join their firm. Own the end-to-end verification process, including verification strategy definition, testbench development, verification item tracking, simulation, and coverage analysis. Develop verification strategies and test plans based on design specifications and microarchitecture. Build and maintain testbenches; perform simulation and debugging to identify, analyze, and resolve design issues and failures. Collaborate closely with Synthesis and Physical Design (PD) teams to debug netlist and timing-related issues, including SDF back-annotation, ensuring design specifications are met. Perform coverage analysis (functional and code coverage) to identify gaps and drive additional verification efforts. Provide clear documentation and reporting, including progress tracking, verification results, and detailed feedback to design teams. Requirements Minimum 5 years of experience in Design Verification (DV). Strong experience across multiple verification levels: IP, Subsystem (SS), and SoC. Proven ability to define and develop verification strategies and test plans. Solid experience in analyzing design specifications and deriving verification item lists. Strong debugging skills, especially for complex designs and corner cases. Hands-on experience with SDF back-annotation simulation and related timing/debug challenges. Good communication skills and ability to collaborate effectively with cross-functional teams. Contact: Giau Nguyen Due to the immense number of applications, only shortlisted candidates will be contacted.