Junior Design Verification Engineer

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Junior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly.

As a Junior Design Verification Engineer, you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of the world's largest AI clusters. If you thrive on solving technical puzzles and want to play a key role in delivering cutting-edge AI infrastructure connectivity, this is your opportunity.

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• Contribute to the design and development of ASIC verification environments, focusing on unit-level and subsystem functional blocks
• Develop and maintain SystemVerilog/UVM-based components including traffic generators, monitors, and checkers to ensure robust testing
• Execute detailed verification plans for challenging digital designs, ensuring all functional requirements are met and verified

• Implement functional coverage models and analyze results to identify gaps in the verification process
• Drive designs toward 100% verification closure through comprehensive test development
• Contribute to verification methodology improvements and best practices

• Work closely with design engineers to identify, root-cause, and resolve complex hardware bugs early in the development cycle
• Apply analytical skills and debugging techniques to solve intricate verification challenges
• Collaborate effectively in a fast-paced, team-oriented R&D environment

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field
• Strong understanding of Digital Logic and at least one programming language (C/C++ or Python)
• Basic familiarity with Verilog or SystemVerilog from academic projects or lab work
• A natural curiosity for "breaking things" and finding bugs, with a strong attention to detail
• Fluent in Hebrew and English with the ability to work effectively in a team environment

• Master's degree in Electrical Engineering or related field
• Basic proficiency in scripting languages such as Python or Tcl to automate verification tasks
• Any prior exposure to UVM/OVM or constrained-random verification is a major plus
• Basic understanding of protocols like PCIe, Ethernet, or DDR