Synthesis Engineer

ACG_3438_JOB Our client is a technology company that is looking for a qualified candidate to join their firm. Lead and execute front-end integration activities including linting, CDC analysis, synthesis, LEC, low-power verification (UPF), formal verification, STA, and ECO implementation. Perform logic and physical synthesis using advanced optimization techniques to generate gate-level netlists optimized for timing, area, and power. Identify and debug issues related to timing, area, and congestion, and collaborate with RTL and physical design teams for resolution. Conduct formal verification between RTL and gate-level netlists; analyze and debug aborts, inconclusive results, and logic equivalence failures. Develop and manage timing constraints for RTL synthesis and STA sign-off at both block and SoC levels; analyze inter-block timing and define I/O timing budgets across partitions. Build, enhance, and maintain synthesis and STA scripts, as well as automation flows to improve efficiency and quality. Collaborate closely with logic design and PnR engineers to resolve issues related to logic, timing, power, and physical implementation. Contribute to technical excellence by supporting reviews, improving methodologies, and ensuring high-quality execution of complex tasks. Provide technical support in customer presentations and internal discussions. Participate in and/or lead technical reviews and peer reviews. Mentor junior engineers to strengthen team capability and knowledge sharing. Requirements Minimum 5 years of experience in synthesis engineering. Solid understanding of ASIC design flow, including Front-End design, DFT, and Place & Route (PnR). Hands-on experience in front-end implementation tasks such as synthesis, constraint development, timing analysis, area/power optimization, linting, and logic equivalence checking. Proficiency with EDA tools: Logic synthesis: DC/FC, Genus RTL/Netlist checking: SpyGlass Lint LEC: Formality, Conformal Low-power verification: VC LP, Conformal LP STA: PrimeTime, Tempus Experience working with multi-clock and multi-power domain designs. Strong scripting/programming skills in languages such as Perl, Python, and Tcl. Knowledge of RTL coding (Verilog/SystemVerilog) or physical design is a plus. Ability to handle complex tasks with high quality and attention to detail. Strong communication skills with the ability to support customer-facing activities. Experience contributing to standard methodologies, documentation, and process improvements. Willingness to mentor junior team members and support team development. Contact: Giau Nguyen Due to the immense number of applications, only shortlisted candidates will be contacted.