Hardware Design Engineering, Senior Director - Active Electric Cable / Smart Cable Module Business
Quick Summary
Electrical/PCB Hardware Design Engineering — schematic capture, high-speed PCB/flex/substrate layout, power delivery,
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Astera Labs is the connectivity backbone of rack-scale AI infrastructure. Our Active Electrical Cables (AEC), Smart Cable Modules (SCM), Silicon Evaluation Platforms, and rack-scale products deliver purpose-built, high-speed connectivity for the world's most demanding AI clusters. As our product portfolio expands in complexity, performance, and volume — and as OEM customers increasingly adopt Astera Labs silicon into their own designs — we need a senior engineering leader to build and scale the hardware design engineering organization that creates industry-defining products and enables our customers' success.
About the Role
~1 min readWe are hiring a Senior Director of Hardware Design Engineering to lead and scale Astera Labs' hardware design engineering organization across Active Electrical Cables (AEC), Smart Cable Modules (SCM), Silicon Evaluation Platforms (SVB/EVB), rack-scale products, and OEM/customer design enablement. This is a senior leadership role with full ownership of the hardware design function — encompassing electrical/PCB design, mechanical engineering, hardware validation, lab infrastructure, and customer hardware engineering support.
You will build and lead a world-class, multidisciplinary engineering organization that takes products from concept through design, validation, qualification, and production release — while simultaneously enabling OEM customers and design partners to successfully integrate Astera Labs silicon into their own products. Your teams will own the complete hardware realization of Astera Labs' connectivity products and serve as the technical bridge between Astera Labs' silicon capabilities and the broader ecosystem of customers building next-generation AI infrastructure.
You will be a key member of the engineering leadership team, driving technology roadmaps, making critical technical and business trade-off decisions, and partnering closely with silicon, firmware, signal integrity, NPI, manufacturing, quality, product management, sales, and customer-facing teams. You'll also be responsible for attracting, developing, and retaining top engineering talent as Astera Labs scales through hyper-growth.
Responsibilities
~1 min read-
Lead and scale Astera Labs' hardware design engineering organization, encompassing:
Requirements
~2 min read-
Lead hardware engineering engagement with OEM customers who are designing Astera Labs silicon into their own products — including hyperscale cloud providers, server OEMs, switch vendors, and cable/module manufacturers
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Provide design review support for customer hardware designs incorporating Astera Labs retimers, re-drivers, and connectivity ASICs — reviewing schematics, layouts, power delivery, thermal solutions, and signal integrity
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Develop and maintain comprehensive reference design packages — including reference schematics, recommended layouts, stackup guidelines, BOM recommendations, thermal design guides, and application notes
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Create and publish hardware design guides, integration manuals, and best-practice documentation that enable OEM customers to achieve first-pass success with Astera Labs silicon
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Establish design review frameworks and checklists that OEM customers can use for self-assessment, supplemented by Astera Labs expert review at critical milestones
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Bachelor's degree in Electrical Engineering, Computer Engineering, or related technical discipline
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18+ years of progressive experience in hardware design engineering for high-speed interconnect, transceiver/module, cable assembly, evaluation platforms, or rack-scale system products
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8+ years in engineering management/leadership roles, including managing managers and building multi-team organizations
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Proven track record leading engineering teams through full product development lifecycle — from concept through qualification and volume production — across product scales from modules to systems
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Deep technical expertise in high-speed PCB/substrate design, signal integrity, power delivery, and mixed-signal circuit design at 56G/112G PAM4 data rates or above
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Strong background in mechanical engineering for interconnect and system products — connector design, thermal management, chassis architecture, and form factor compliance
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Demonstrated experience establishing and executing hardware validation and qualification programs for high-reliability products
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Experience building and managing hardware engineering lab infrastructure and measurement capabilities
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Master's or Ph.D. in Electrical Engineering with emphasis on high-speed interconnects, electromagnetic design, or mixed-signal systems
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Direct experience developing Active Electrical Cables (AEC), Smart Cable Modules (SCM), optical transceivers, or high-speed cable/connector assemblies
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Experience designing silicon evaluation platforms (EVBs/SVBs) for complex SoCs, ASICs, or connectivity silicon
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Experience developing rack-scale or chassis-class hardware products for data center, hyperscale, or AI infrastructure applications (switch chassis, OCP systems, or equivalent)
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Build and lead a customer hardware engineering support function that provides responsive, expert-level technical assistance to OEM customers during their design and integration cycles
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Support customer bring-up, debug, and troubleshooting activities — providing hands-on engineering engagement when customers encounter hardware integration challenges with Astera Labs silicon
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Drive resolution of customer-reported hardware issues — coordinating across internal teams (silicon, firmware, SI, validation) to provide root cause analysis and corrective guidance
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Establish escalation processes and service-level expectations for customer hardware engineering support, ensuring timely and high-quality responses
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Travel to customer sites as needed to provide on-site design review, debug support, or integration assistance for critical programs
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Serve as the bridge between Astera Labs' internal product designs and the external ecosystem of customers building with Astera Labs silicon — ensuring learnings flow bidirectionally
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Capture common customer design challenges, failure modes, and best practices — feeding these back into reference designs, design guides, evaluation platforms, and silicon requirements
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Partner with Sales, FAE, and Product Management teams to identify high-value customer engagements and prioritize hardware engineering support resources
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Collaborate with silicon design teams to provide hardware-level feedback on package design, pin assignment, power requirements, and thermal specifications based on customer and internal design experience
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Support joint development programs with strategic OEM partners — including co-designed products, custom form factors, and platform-specific optimizations
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Partner closely with Signal Integrity engineering to ensure designs meet channel performance requirements and simulation-to-measurement correlation is maintained
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Collaborate with Firmware Engineering to ensure hardware-firmware co-design — including power sequencing, thermal management, CMIS interface implementation, BMC integration (for rack-scale products), and diagnostic feature support
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Work with NPI and Manufacturing Engineering to ensure designs are manufacturable, testable, and scalable at volume — participating in DFM/DFA/DFT reviews and supporting production ramp across CMs and ODMs
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Engage with Quality and Reliability teams to ensure products meet Astera Labs' quality standards and customer reliability expectations
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Interface with Product Management to align development priorities with market opportunities, customer requirements, and business objectives
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Partner with Sales and FAE teams to support customer design-in activities, provide technical differentiation during competitive evaluations, and ensure customer success drives revenue growth
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Support Customer Engineering and Applications teams in resolving platform integration issues and driving design improvements based on field feedback
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Collaborate with Silicon Engineering to ensure evaluation platforms provide optimal silicon bring-up, characterization, and demonstration capabilities — and that customer hardware integration feedback informs future silicon development
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Ensure hardware designs comply with relevant industry standards — IEEE 802.3ck/dj, OIF CEI-112G/224G, SFF-TA (OSFP, QSFP-DD), CMIS, OCP specifications, and emerging rack-scale standards
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Represent Astera Labs in industry standards bodies, MSAs, and technical working groups as appropriate
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Monitor competitive landscape, emerging technologies, and standards evolution to inform roadmap and design decisions
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Engage with OEM customers and industry partners on pre-standard technologies and next-generation specifications
Proven ability to make both strategic technology decisions and detailed technical trade-offs that balance performance, cost, schedule, and manufacturability
Experience managing engineering teams through hyper-growth — scaling organizations, processes, and infrastructure simultaneously
Strong executive communication skills — able to present technology strategy, program status, and risk assessments to C-level leadership and customer executives
Experience partnering with contract manufacturers and ODMs in Asia for hardware product realization
Experience with 224G/lane (1.6T aggregate) interconnect technology and next-generation substrate/connector/cable architectures
Track record delivering connectivity products to hyperscale customers (AWS, Google, Microsoft, Meta, NVIDIA, or equivalent) for AI/ML infrastructure applications
Experience integrating retimer ASICs into cable module or system-level products
Deep familiarity with relevant standards: IEEE 802.3ck/dj, OIF CEI-112G/224G, SFF-8636, CMIS 5.x+, OSFP, QSFP-DD, OCP specifications
Experience with rack-scale system design including power distribution, thermal/airflow architecture, BMC/management interfaces, and high-density backplane/midplane design
Background in FMEA, DFMEA, robust design methodologies, and six-sigma quality approaches
Mandarin language proficiency for direct engagement with manufacturing partners in China
Experience with simulation and EDA tools (Cadence Allegro/OrCAD, Ansys HFSS/SIwave, Keysight ADS, SolidWorks/Creo, thermal/CFD simulation tools)
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
Location & Eligibility
Listing Details
- Posted
- June 3, 2026
- First seen
- June 4, 2026
- Last seen
- June 4, 2026
Posting Health
- Days active
- 0
- Repost count
- 0
- Trust Level
- 60%
- Scored at
- June 4, 2026
Signal breakdown
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