Quick Summary
Collaborate with cross-functional teams to clarify and comprehend intricate design specifications and requirements. Architect and implement advanced micro-architectures from high-level specifications for silicon components, adhering to performance,…
Axelera AI is not your regular deep-tech startup. We are creating the next-generation AI platform to support anyone who wants to help advancing humanity and improve the world around us.
In just four years, we have raised a total of $370 million and have built a world-class team of 220+ employees (including 49+ PhDs with more than 40,000 citations), both remotely from 18 different countries and with offices in Belgium, France, Switzerland, Italy, the UK, headquartered at the High Tech Campus in Eindhoven, Netherlands.
We have also launched our Metis™ AI Platform, which achieves a 3-5x increase in efficiency and performance, and have visibility into a strong business pipeline exceeding $100 million.
Our unwavering commitment to innovation has firmly established us as a global industry pioneer.
Are you up for the challenge?
As a Logical Design Engineer, you will join a team responsible for the micro-architecture, implementation and execution of in-house designed AI products. Your role will be critical in achieving the highest level of quality and performance as well as ensuring continued innovation in both design and design flow. This is an opportunity to work with cutting-edge technology and a dedicated team of professionals who share your passion for pushing the boundaries of what's possible.
Responsibilities
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Collaborate with cross-functional teams to clarify and comprehend intricate design specifications and requirements.
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Architect and implement advanced micro-architectures from high-level specifications for silicon components, adhering to performance, power, and area (PPA) metrics.
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Employ industry-standard design tools and methodologies to fashion and optimize digital logic circuits.
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Conduct block and system-level RTL coding, ensuring optimal performance, power, and area (PPA) metrics.
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Integrate various IPs/Sub IPs into the top-level SoC.
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Perform static checks (lint, cdc, equivalence checks) to enhance the quality of the RTL.
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Automate tasks using scripting for efficiency gains.
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Undertake comprehensive functional verification and collaborate closely with verification engineers to ensure the correctness of the design.
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Actively engage in design reviews, contributing technical expertise to enhance overall design quality.
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Work collaboratively with physical design engineers to address design-for-manufacturability (DFM) and design-for-test (DFT) considerations.
Requirements
~1 min readWe offer a flexible working arrangement, with options to:
Work from one of our Axelera AI offices (Leuven in Belgium, Amsterdam and Eindhoven in the Netherlands, Zurich in Switzerland, Florence and Milan in Italy or Bristol in the United Kingdom) if you're already based in the vicinity.
Work fully remotely from any European country (incl. the UK) you are already in.
Relocate with us and work from Italy (Florence or Milan) or the Netherlands (Amsterdam or Eindhoven).
What We Offer
~1 min readThis is your chance to shape and be part of a dynamic, fast-growing, international organization. We offer an attractive compensation package, including a pension plan, extensive employee insurances and the option to get company shares.
An open culture that supports creativity and continual innovation is awaiting you. Collaborative ownership and freedom with responsibility is characteristic for the way we act and work as a team.
At Axelera AI, we wholeheartedly embrace equal opportunity and hold diversity in the highest regard. Our steadfast commitment is to cultivate a warm and inclusive environment that empowers and celebrates every member of our team. We welcome applicants from all backgrounds to join us in shaping the future of AI.
Location & Eligibility
Listing Details
- Posted
- January 22, 2026
- First seen
- May 5, 2026
- Last seen
- May 8, 2026
Posting Health
- Days active
- 0
- Repost count
- 0
- Trust Level
- 23%
- Scored at
- May 6, 2026
Signal breakdown
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