Staff Engineer, IP Design (ASIC)

You will join the System on Chip (SoC) Design Team at SK Hynix memory solutions America, a group dedicated to delivering best-in-class controllers for high-performance SSDs. This team spans the full design cycle—from micro-architecture and RTL design to timing closure and tapeout readiness—enabling next-generation enterprise and AI data center storage solutions. As a Staff Engineer, you will own critical High speed interface IP, drive methodology improvements (such as AI-assisted design flows), and mentor engineers to ensure first-pass silicon success.

• →Design and verification of the high speed interface for next generation storage subsystem for NVME or Chiplet.
• →Drive team efforts with multi-function teams from RTL development through silicon bring-up.

• 8 years of experience in ASIC design and deep knowledge in the design and integration of PCle logic.
• Experience debugging RTL using Verdi/VCS and automating tasks via Python or Perl.
• Experience in SystemVerilog/Verilog for RTL development and microarchitecture definition.
• Experience with Clock Domain Crossing (CDC), timing closure, or synthesis flows.

• Experience in PCle(Gen4/5/6) architecture in TLP/FLIT pipelines, flow control, ordering rules, and performance tuning.
• Proven experience with Link training, power state(L0/L0P/L1/L2), error handling (AER).
• Experience with cross-functional leadership, driving efforts with software/system teams from RTL development through silicon bring-up.
• Good plus to have experience in AI Assist design flow.

•  Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.