Developer (Design Verification Engineer)

1. Develop SystemVerilog testbenches and UVM-based verification environments to validate complex digital designs. The chance to use your skills and imagination to push the boundaries of what´s possible. To build solutions never seen before to some of the world's toughest problems. You´ll be challenged, but you won't be alone. You´ll be joining a team of diverse innovators, all driven to go beyond the status quo to craft what comes next. What happens once you apply? Click Here to find all you need to know about what our typical hiring process looks like. We truly believe this approach drives innovation, which is essential for our future growth. DISCLAIMER: The above statements are intended to describe the general nature and level of work being performed by employees in this position. They are not an exhaustive list of all responsibilities, duties and skills required for this position, and you may be required to perform additional job tasks as assigned. Primary country and city: United States (US) || Austin (Country/ City) Job details: Developer Job Stage: Job Stage 6 Primary Recruiter: Avinash Kumar Designing and implementing constrained-random and directed test cases to ensure comprehensive functional coverage.