Senior FPGA Engineer - Quantum Networking
Quick Summary
Develop, implement, and verify VHDL/Verilog firmware for Field-Programmable Gate Arrays (FPGAs) focusing on the real-time classical control channel.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related engineering discipline. 5+ years of experience (or equivalent) in high-speed,
IonQ, Inc. [NYSE: IONQ] is the world’s leading quantum platform and merchant supplier - delivering integrated quantum solutions across computing, networking, sensing, and security. IonQ’s newest generation of quantum computers, the IonQ Tempo, is the latest in a line of cutting-edge systems that have been helping customers and partners including Amazon Web Services, and AstraZeneca achieve 20x performance results and accelerate innovation in drug discovery, materials science, financial modeling, logistics, cybersecurity, and defense. In 2025, the company achieved 99.99% two-qubit gate fidelity, setting a world record in quantum computing performance.
Headquartered in College Park, Maryland, IonQ has operations in California, Colorado, Massachusetts, Tennessee, Washington, Italy, South Korea, Sweden, Switzerland, Canada, and the United Kingdom. Our quantum computing services are available through all major cloud providers, while we also meet the needs of networking and sensing customers across land, sea, air, and space. IonQ is making quantum platforms more accessible and impactful than ever before.
We are looking for a Senior Real-Time Embedded Systems Engineer to join our team. As a Senior Engineer, you’ll be part of a cross-functional team whose mission is to lead IonQ on its journey to build the world’s best quantum computers and networked systems to solve the world’s most complex problems.
In this role, you will focus on the Real-Time Classical Channel, developing the embedded logic necessary to synchronize and control quantum operations at nanosecond precision. You will be responsible for the firmware and logic running on FPGAs to handle critical tasks like nanosecond-level synchronization and "Repeat-Until-Success" feedback loops. This position is essential for providing the hardware abstraction layer that enables the quantum node’s operating system to function.
Responsibilities
~1 min read- →Develop, implement, and verify VHDL/Verilog firmware for Field-Programmable Gate Arrays (FPGAs) focusing on the real-time classical control channel.
- →Implement nanosecond-level synchronization protocols (e.g., White Rabbit-PTP) to maintain sub-nanosecond precision across distributed hardware systems.
- →Design and optimize hardware triggers for immediate photon generation and detection events.
- →Engineer the logic necessary for high-speed, low-latency “Repeat-Until-Success” feedback loops critical for quantum operations.
- →Define and provide the hardware abstraction layer (registers, interrupts, and memory-mapped controls) consumed by the higher-level QNodeOS developers.
- →Collaborate closely with Hardware Engineers to understand board timing constraints, signal paths, and low-level control requirements.
- →Own the full FPGA development lifecycle from specification and RTL design to testing, timing closure, and system integration.
- →Drive technical decisions on timing architectures and control strategies for the real-time embedded system.
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related engineering discipline.
- 5+ years of experience (or equivalent) in high-speed, real-time embedded systems design and FPGA development.
- Deep expertise in RTL design (VHDL or Verilog) and validation for complex, high-performance FPGAs (e.g., Xilinx or Intel).
- Proven experience implementing precise timing and synchronization protocols, such as PTP (Precision Time Protocol), or low-jitter clock distribution networks.
- Experience designing systems with sub-microsecond or nanosecond timing constraints.
- Proficiency in utilizing simulation and synthesis tools for timing closure and formal verification.
- Strong understanding of the complete hardware/software interface, including memory-mapped registers, DMA, and interrupt handling.
- Experience with low-latency communication interfaces (e.g., 10G/40G Ethernet, JESD204B).
- Experience implementing feedback loops or active stabilization systems in real-time firmware.
- Familiarity with hardware/software co-design principles and embedded Linux environments.
- Knowledge of quantum computing, high-precision physics experiments, or photon detection systems.
Requirements
~1 min readIf you are interested in being a part of our team and mission, we encourage you to apply!
Listing Details
- First seen
- March 26, 2026
- Last seen
- April 21, 2026
Posting Health
- Days active
- 26
- Repost count
- 0
- Trust Level
- 31%
- Scored at
- April 21, 2026
Signal breakdown
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