ASIC Engineer

Object Technology Solutions, Inc (OTSI) has an immediate opening for ASIC Engineer 4 ASIC Engineer 4 (onsite, Minneapolis, MN ) MAJOR RESPONSIBILITES: • Floorplanning: Define and implement the full chip floorplan in close collaboration with the analog design team — including custom analog block placement, analog/digital partitioning, I/O ring architecture, power domain definition, and block-level area allocation. • Power Planning: Design and implement the chip power distribution network (PDN); coordinate with the analog team on analog supply isolation, guard ring placement, and substrate noise considerations. • Place & Route: Execute full-chip place-and-route (Cadence Innovus) from synthesized netlist through routed and optimized database across all required corners and modes. • Timing Closure: Own static timing analysis (Cadence Tempus) across all PVT corners and modes; identify and resolve timing violations through ECO, placement, and routing optimization; coordinate with the Chip Lead on constraint refinement. • Power Integrity: Perform IR drop and electromigration analysis (Cadence Voltus or equivalent); identify and resolve PDN weaknesses. • Physical Verification Sign-off: Execute and close DRC, LVS, and ERC to foundry-clean status using Mentor Calibre; manage waiver process for any non-cleanable violations. • DFT Integration: Implement scan chain insertion and work with the Chip Lead on ATPG pattern generation and test coverage targets. • Foundry Coordination: Interface with foundry on PDK questions, fill rule implementation, and tape-out submission requirements. Documentation: Maintain PD methodology documentation, floorplan rationale records, and ECO history to support program continuity and knowledge transfer at contract close. GDSII tape-out sign-off is the primary deliverable of this contract SKILLS AND ABILITIES REQUIRED: • Experience with mixed-signal or analog-adjacent chip physical design — including analog supply domain implementation, substrate isolation techniques, and analog/digital floor separation • Familiarity with high-speed I/O pad ring design for differential full-duplex interfaces • Experience with power domain implementation using UPF/CPF for multi-voltage PHY designs • Proficiency with Cadence Voltus or Apache Redhawk for power integrity analysis • Familiarity with Synopsys IC Compiler 2 (ICC2) as an alternative P&R environment • Experience with signoff ECO flows — functional and metal-only ECOs post-tape-out • Prior contract or startup experience — comfort operating where role boundaries are defined by program need rather than org chart • QUALIFICATIONS AND EXPERIENCE: • BS, MS, or PhD in Electrical Engineering or related field • 8–15 years of physical design experience with at least one complete front-to-back tape-out as the primary or lead PD engineer • Hands-on proficiency with Cadence Innovus for place-and-route — comfortable navigating complex placement constraints, congestion-driven routing, and post-route optimization without step-by-step guidance • Hands-on proficiency with Cadence Tempus for static timing analysis including MMMC setup, OCV/AOCV analysis, and ECO-driven timing closure • Hands-on proficiency with Mentor Calibre for DRC, LVS, and ERC sign-off • Experience placing and integrating hard macros (analog PHY blocks, memory compilers, I/O cells) within a constrained mixed-signal floorplan • Demonstrated ability to take broad ownership and drive to closure — comfortable leading implementation decisions, working across disciplines, and managing priorities without a large supporting PD organization • Strong debugging and root-cause analysis skills — the ability to look at a failing DRC deck, a congested routing region, or a timing path that doesn’t respond to standard approaches and find a path forward • Ability to hit the ground running — this engagement has a fixed end date tied to tape-out; ramp time is minimal by design • Clear communicator across disciplines — able to discuss physical implementation constraints and their design implications with Chip Lead, analog designers, and verification engineers • Proven end-to-end tape-out ownership • Experience taking designs from concept through tape-out independently • Ability to work with incomplete or evolving specifications • Comfortable with new technology and undefined flows • Self-starter with ability to operate under minimal oversight • Capable of managing multiple design phases in a resource-constrained environment. • High ownership, low support structure • Self-driven execution required • Ability to function effectively with ambiguity and evolving requirements About us: About Us OTSI is a global technology partner providing enterprise IT consulting, digital solutions, and managed services. We help organizations modernise complex technology landscapes, harness the power of data, and build scalable AI-led ecosystems to accelerate innovation and business growth. With over 26 years of experience, we consistently turn complex challenges into success stories through our strong technical capabilities and deep industry knowledge. Our global team of 1,800+ professionals, spread across 6 countries, delivers cutting-edge solutions for customers across Banking, Financial Services, Insurance, Transportation & Logistics, Energy & Utilities, Healthcare & Life Sciences, Government, Hi-Tech, Telecom & Media, Manufacturing, and more. Our focused technologies are: Data & Analytics (Traditional EDW, BI, Big data, Data Engineering, Data Management, Data Modernization, Data Insights) Digital Transformation (Cloud Computing, Mobility, Micro Services, RPA, DevOps) QA & Automation (Manual Testing, Non-functional testing, Test Automation, Digital Testing) Enterprise Applications (SAP, Java Full stack, Microsoft, Custom Development) Disruptive Technologies (Edge Computing/IOT, Block Chain, AR/VR, Biometric)