Graduate Server CPU Physical Design Engineer - Cambridge, UK

About Us

Qualcomm is seeking talented Graduate Server CPU Physical Design Engineers to join the Nuvia Data Centre CPU team in Cambridge, UK. The team is developing next-generation, high-performance, power-efficient custom CPU cores for advanced compute and server-class platforms that will help transform the industry.

About the role

This is an exciting opportunity for graduates who want to start their engineering career working on cutting-edge CPU technology. You will learn from experienced engineers and contribute to the physical implementation of high-performance CPU designs, gaining exposure to the full journey from RTL/netlist through implementation, timing closure, signoff, and silicon delivery.

You will work with global teams across CPU architecture, RTL design, circuit design, CAD, SoC integration, timing, power, and post-silicon validation. Over time, you will develop the skills needed to contribute to demanding performance, power, and area — PPA — targets for advanced server-class CPU products.

This role is designed for recent graduates or early-career engineers with strong fundamentals in digital design, VLSI, computer architecture, semiconductor design, or physical implementation.

As a Graduate Server CPU Physical Design Engineer, you will:

• →Learn and contribute to CPU block physical implementation from RTL/netlist to GDS, including synthesis, floorplanning, placement, clock tree synthesis — CTS — routing, optimization, ECOs, and signoff.
• →Support timing closure and implementation convergence across multiple modes, corners, and operating conditions.
• →Work with experienced engineers to analyse and improve performance, power, and area — PPA — for high-performance, low-power CPU designs.
• →Help debug physical design issues related to timing, congestion, routing, clocking, power, physical verification, DRC/LVS, and ECO closure.
• →Use industry-standard EDA tools and flows for synthesis, place and route, static timing analysis, power analysis, and physical verification.
• →Develop scripting and automation skills to improve productivity, data analysis, and design-flow efficiency.
• →Collaborate with RTL, architecture, CAD, circuits, SoC, and post-silicon teams to understand design intent and implementation trade-offs.
• →Learn how CPU designs progress from early concept through implementation, verification, signoff, and productization.
• →Contribute to methodology improvements, automation, documentation, and data-driven analysis under the guidance of senior engineers.

In this role, you will develop practical expertise in:

• →Server CPU physical design and implementation methodology.
• →RTL/netlist to GDS implementation flows.
• →Synthesis, floorplanning, placement, CTS, routing, ECOs, and signoff.
• →Static timing analysis and timing closure.
• →Power, area, congestion, and routability trade-offs.
• →Physical verification and design quality checks.
• →Advanced-node implementation challenges.
• →Automation and scripting for design-flow productivity.
• →Cross-functional collaboration across CPU design, CAD, circuits, SoC, and post-silicon teams.

We are looking for graduates or early-career engineers with strong academic foundations and a passion for CPU, ASIC, or semiconductor design.

The ideal candidate will have:

• Good understanding of digital logic design, CMOS fundamentals, VLSI design, or semiconductor design concepts.
• Basic understanding of static timing analysis concepts, including setup, hold, clocking, timing paths, and timing constraints.
• Exposure to scripting or programming using one or more of: TCL / Python / Perl
• Strong analytical and problem-solving skills.
• Ability to learn complex technical concepts quickly and apply them in a practical engineering environment.
• Good communication skills and willingness to work in a collaborative, global engineering team.

Experience or exposure in any of the following areas would be advantageous, but is not mandatory:

• University coursework, internship, thesis, or project work in VLSI, ASIC design, physical design, digital IC design, computer architecture, or EDA.
• Familiarity with EDA tools used for synthesis, place and route, STA, power analysis, or physical verification.
• Experience with Verilog/SystemVerilog, digital logic design, or RTL concepts.
• Understanding of CPU architecture, pipelines, caches, clocking, or low-power design concepts.
• Experience using Linux-based engineering environments.
• Data analysis skills and ability to work with reports, logs, metrics, and design results.
• Curiosity about how high-performance CPU designs are physically implemented and optimized.

Candidates should typically have one of the following:

• Bachelor’s degree in Electrical Engineering, Electronic Engineering, Computer Engineering, Computer Science, or a related technical field.

• Master’s degree in Electrical Engineering, Electronic Engineering, Computer Engineering, Computer Science, Microelectronics, Semiconductor Engineering, or a related technical field.

• PhD in a relevant technical field with research or project experience related to digital design, VLSI, ASIC implementation, CPU design, or semiconductor design.

Recent graduates and candidates with internship, industrial placement, academic research, or project experience in relevant areas are encouraged to apply.

We are especially interested in graduates who:

• Have strong engineering fundamentals and a passion for semiconductor design.
• Enjoy solving complex technical problems.
• Are curious about CPU design, physical implementation, and advanced Compute platforms.
• Can learn quickly and take ownership of technical tasks.
• Bring a structured, analytical approach to debugging and problem-solving.
• Communicate clearly and collaborate effectively with others.
• Are motivated by the opportunity to build high-performance, power-efficient server CPU products.
• Demonstrate initiative, curiosity, attention to detail, and a continuous-improvement mindset.