Sr. PCIe PHY Validation Engineer
United States·San Jose,San JosemidQuick Summary
Define validation goals, objectives, and metrics to ensure product performance and compliance. Develop and execute comprehensive test plans for SerDes interfaces (PCIe).
Coding experience with programming and scripting languages such as C/C++, JS and Python. Signal and Power Integrity Knowledge.
About the Role
~1 min readAs a High Speed SerDes Validation Engineer, you will own the end-to-end electrical compliance and performance optimization for our enterprise SSD (eSSD) portfolio. You will lead the efforts to secure PCISIG PCIe Gen 5 (and upcoming Gen 6) Integrator List official certification. This role is critical to ensuring our high-speed SerDes architectures deliver maximum data throughput and reliability across next-generation data center servers.
Responsibilities
~1 min read- →Signal and Power Integrity Knowledge.
Location & Eligibility
Listing Details
- Posted
- May 15, 2026
- First seen
- May 17, 2026
- Last seen
- June 19, 2026
Posting Health
- Days active
- 33
- Repost count
- 0
- Trust Level
- 23%
- Scored at
- June 19, 2026
Signal breakdown
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