Junior Physical Design Engineer

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Junior Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters.

As a Junior Physical Design Engineer, you will be a key architect of our silicon's physical reality. You won't just execute a flow—you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets required for next-generation AI infrastructure. If you thrive on solving complex challenges in deep-submicron processes and want to shape the backend methodology for AI infrastructure connectivity, this is your opportunity.

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• Be part of the founding Backend team in Israel, playing a critical role in establishing local execution culture and technical standards
• Take full responsibility for physical implementation journey including Synthesis, Floorplanning, Place & Route, and Clock-Tree Synthesis (CTS)
• Own macro-level implementation with deep hands-on experience in floorplanning and complex routing

• Drive final stages of design integrity, owning Timing signoff (STA), Physical Verification (DRC/LVS), and Reliability analysis (EMIR)
• Ensure first-pass silicon success through rigorous signoff flows and analysis
• Apply Logic Equivalence Checking (LEC) and other verification techniques to guarantee design correctness

• Participate in defining and refining Backend methodologies with autonomy to improve workflows and tool automation
• Work closely with Architecture, Design, and DFT teams to navigate challenges of advanced process nodes and high-speed connectivity
• Leverage scripting and automation to make engineering environment faster and more robust

• Experience with full-chip level implementation and integration
• Knowledge of Power and Noise analysis (SI/PI) to optimize high-performance silicon
• Familiarity with Design-for-Test (DFT) requirements and their impact on physical layout
• Experience with industry-standard EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus)
• Background in high-speed interface designs or connectivity protocols