HW Design Verification Intern
Quick Summary
At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.
You will work alongside a team building state-of-the-art LLM inference SoCs, gaining hands-on exposure to modern compute units, crossbars, chiplet interconnects, and high-performance memory interfaces.
At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.
We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI.
Hybrid, working onsite at our Santa Clara office 3 days per week.
12 Week Program: June 1st - August 21st or June 22nd - September 11th
Responsibilities
~1 min readYou will work alongside a team building state-of-the-art LLM inference SoCs, gaining hands-on exposure to modern compute units, crossbars, chiplet interconnects, and high-performance memory interfaces.
In this role,
- →
You’ll contribute to the functional verification of complex hardware blocks using UVM-based methodologies and
- →
Accelerate bug-finding with formal verification techniques using SystemVerilog Assertions (SVA).
- →
You’ll also develop and maintain tools that improve simulation efficiency and verification productivity, and
- →
Help explore how emerging AI-assisted workflows can strengthen DV methodology.
Responsibilities
~1 min read- →
Pursuing a Master’s or PhD degree in Electrical and Computer Engineering, or a related scientific discipline
- →
Relevant coursework in Computer Architecture, Verilog, and/or FPGA development
- →
Familiarity with the SystemVerilog programming language (required)
- →
Familiarity with SystemVerilog Assertions (SVA) (preferred, not required)
- →
Current knowledge of AI SoC and/or LLM inference architectures (preferred, not required)
- →
Excellent verbal and written communication skills
d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.
d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.
Location & Eligibility
Listing Details
- Posted
- March 6, 2026
- First seen
- May 6, 2026
- Last seen
- May 8, 2026
Posting Health
- Days active
- 0
- Repost count
- 0
- Trust Level
- 28%
- Scored at
- May 6, 2026
Signal breakdown
Please let d-matrix know you found this job on Jobera.
Similar Design Verification Engineer jobs
View all →Browse Similar Jobs
Stay ahead of the market
Get the latest job openings, salary trends, and hiring insights delivered to your inbox every week.
No spam. Unsubscribe at any time.