Head of Performance Visibility

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  Define the architectural approach for collecting and structuring telemetry across CPUs, drivers, interconnects, and multiple accelerators

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  Design scalable models for correlating performance events across device and host boundaries

• Develop mechanisms to align hardware counters, runtime activity, communication phases, and workload semantics across model-layer execution into coherent, actionable insight

• Implement time synchronization and trace-alignment strategies across multi-device systems

• Define structured counter taxonomies separating base signals from derived metrics

• Design derived performance models bridging low-level hardware signals and workload-level behavior

• Influence instrumentation strategy for future hardware generations

• Build tools that identify bottlenecks among multi-accelerator workloads across chips within hosts

• Build cluster-scale performance analysis for distributed inference across data center networks

• Contribute to analysis engines and developer-facing tooling that transform raw telemetry into intuitive insight

• Shape how performance intelligence is surfaced to engineers debugging large-scale AI systems

• Deep experience building complex systems at the intersection of hardware and software

• Personally envisioned and built significant portions of profiling, tracing, or observability systems — not solely defined requirements or product strategy

• Demonstrated ability to translate raw hardware signals into scalable, production-grade telemetry and analysis infrastructure

• Experience correlating time-series events across distributed systems

• Deep systems programming expertise (C++ or Rust), with a track record of shipping low-level infrastructure operating close to hardware or runtime systems

• Experience designing distributed correlation mechanisms, timestamp-alignment strategies, or performance modeling frameworks across multiple devices or hosts

• Experience designing distributed tracing or observability platforms at scale

• Experience with high-performance computing systems and large AI training clusters

• Experience with timestamp synchronization strategies and event alignment in distributed environments

• Experience with hardware counter design and instrumentation strategy

• Experience with performance modeling for large-scale ML workloads

• Experience leading cross-functional architectural initiatives spanning hardware and software teams

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.