S
USD 150000-260000/yr

3D Stacked DRAM Design Engineer

United StatesUnited States·San Josemid
EngineeringDesign Engineer
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Quick Summary

Key Responsibilities

Design high-speed digital IP design for 3D-stacked DRAM peripheral circuits and DRAM DFT with U.S.-based customers (including RTL design to implementation).

Requirements Summary

Design high-speed digital IP design for 3D-stacked DRAM peripheral circuits and DRAM DFT with U.S.-based customers (including RTL design to implementation).

Technical Tools
EngineeringDesign Engineer

To strengthen leadership in the DRAM-on-Logic era through optimized DRAM die design, we are seeking talent capable of driving the co-design of 3D-stacked DRAM logic dies in close collaboration with U.S.-based customers. This strategic hiring initiative aims to enhance our global competitiveness by fostering deep engagement with key American clients, ensuring that our die design solutions are precisely aligned with their evolving technical requirements and market demands.

Responsibilities

~1 min read
  • Design high-speed digital IP design for 3D-stacked DRAM peripheral circuits and DRAM DFT with U.S.-based customers (including RTL design to implementation).
  • Engage in foundry verification of service-ready IPs and infrastructure setup for IP business.
  • Co-develop next-generation DRAM-on-Logic solutions with key customers to enhance our service competitiveness and market position.
  • Strengthen competitiveness through sustained customer collaboration and technical leadership.

Requirements

~1 min read
  • Bachelor’s degree or higher in Electrical Engineering or a related discipline with 4+ years of relevant experience.
  • Development of DRAM and design DRAM circuit based on custom design methodology (using virtuoso [or similar tools], spice simulator).
  • Experience reviewing DRAM specifications and architecture.
  • Circuit design experience to meet internal and external requirements for DRAM products.
  • Experience evaluating compliance with DRAM specifications through design analysis at the wafer levels test / package levels test / system level test.
  • Experience in full custom + digital Co-design and PDN analysis.
  • Experience in full custom-based logic foundry design.
  • Expert in Python, and circuit simulators (HSPICE, PrimeSim, Spectre, etc.).
  • Excellent verbal and written communication in English; ability to present technical concepts to cross functional teams and senior management.

What We Offer

~1 min read
Top Tier health insurance at no employee cost
Paid day offs: PTO + Company Holidays + Happy Fridays
Paid Parental Leave Program
401k Matching
Educational reimbursement up to $10,000 per year for job-related higher education degree
Donation Matching and volunteering opportunities
Corporate discount programs
Free Breakfast/Lunch/Dinner provided to employees

SKHYA is an Equal Employment Opportunity Employer. We provide equal employment opportunities to all qualified applicants and employees and prohibit discrimination and harassment of any type without regard to race, sex, pregnancy, sexual orientation, religion, age, gender identity, national origin, color, protected veteran or disability status, genetic information or any other status protected under federal, state, or local applicable laws. 

Location & Eligibility

Where is the job
San Jose, United States
On-site at the office
Who can apply
US

Listing Details

Posted
July 17, 2026
First seen
July 17, 2026
Last seen
July 17, 2026

Posting Health

Days active
0
Repost count
0
Trust Level
79%
Scored at
July 17, 2026

Signal breakdown

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S
3D Stacked DRAM Design EngineerUSD 150000-260000