3D Stacked DRAM-on-Logic Design Engineer

To strengthen leadership in the DRAM-on-Logic era through optimized DRAM die design, we are seeking talent capable of driving the co-design of 3D-stacked DRAM logic dies in close collaboration with U.S.-based customers. This strategic hiring initiative aims to enhance our global competitiveness by fostering deep engagement with key American clients, ensuring that our die design solutions are precisely aligned with their evolving technical requirements and market demands.

• →Strengthen leadership in the DRAM-on-Logic Era through advanced digital IP design for 3D-Stacked DRAM.
• →Provide digital IP services for 3D-stacked DRAM to enable DRAM-on-Logic system configurations for customers.
• →Establish close technical engagement with foundry companies to build digital IP of 3D-stacked DRAM.

• Bachelor’s degree or higher in Electrical Engineering or a related discipline with 5+ years of relevant experience.
• Development of Digital Logic IP/SoC based on Hardware Description Languages (Verilog, VHDL).
• Experience in RTL design and implementation memory PHY, hard macro IP for high-speed circuit, or high-speed digital IP design.
• Experience with memory controllers.
• Experience in memory Built-in Self-Test (BIST), DRAM Design for Test (DFT) / Design for Debug (DFD).
• Deep understanding of PPA analysis and optimization, and physical design.
• Excellent verbal and written communication in English; ability to present technical concepts to cross functional teams and senior management.

SKHYA is an Equal Employment Opportunity Employer. We provide equal employment opportunities to all qualified applicants and employees and prohibit discrimination and harassment of any type without regard to race, sex, pregnancy, sexual orientation, religion, age, gender identity, national origin, color, protected veteran or disability status, genetic information or any other status protected under federal, state, or local applicable laws.