Sr. Principal Engineer, IP Design (ASIC)

You will join the System on Chip (SoC) Design Team at SK hynix memory solutions America, a group dedicated to delivering best-in-class controllers for high-performance SSDs. This team spans the full design cycle—from micro-architecture and RTL design to timing closure and tapeout readiness—enabling next-generation enterprise and AI data center storage solutions. As a Senior Principal Engineer, you will own critical IP blocks end-to-end, drive methodology improvements (such as AI-assisted design flows), and mentor staff engineers to ensure first-pass silicon success.

• →Lead End-to-End IP Ownership: Architect, design, and verify complex IP blocks or subsystems for high-performance memory controllers, taking ownership from specification to tapeout.
• →RTL Design & Integration: Develop efficient, high-speed RTL (Verilog/SystemVerilog) for critical modules, ensuring optimization for power, performance, and area (PPA).
• →Design Verification & Quality: Oversee design reviews, linting, Clock Domain Crossing (CDC) analysis, and power analysis to ensure robust functional and timing closure.
• →Cross-Functional Leadership: Collaborate deeply with verification, DFT, physical design, and firmware teams to resolve complex system-level bottlenecks and ensure seamless integration.
• →Methodology Innovation: Drive enhancements in design automation (Python/Tcl/Perl) and best practices for synthesis and static timing analysis (STA) to improve team efficiency.
• →Mentorship: Mentor junior and staff engineers on advanced design techniques, code quality, and debugging strategies.

• Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.
• Experience: 12+ years of hands-on experience in ASIC/SoC design with a proven track record of successful tapeouts.
• Technical Mastery: Expert proficiency in Verilog/SystemVerilog, logic design, synthesis, and STA for high-speed digital circuits.
• Tool Proficiency: Strong experience with industry-standard EDA tools (Synopsys/Cadence) for simulation, linting, and CDC analysis.
• Communication: Demonstrated ability to lead technical discussions and document complex micro-architectures clearly for cross-functional teams.

• Advanced Education: Master’s or PhD in Electrical Engineering with 8+ years of applicable experience.
• Domain Knowledge: Deep understanding of memory controller architectures (PCIe/NVMe, DDR, NAND Flash) or error correction algorithms.
• High-Speed Design: Experience designing for high-frequency interfaces or data center/enterprise applications.
• Scripting/Automation: Proficiency in Python, Tcl, or Perl for design automation and flow optimization.
• Leadership: Previous experience serving as a technical lead or architect for a major subsystem or IP block.

• Enterprise SSD Controllers for AI/Data Centers: Designing best-in-class SoCs tailored for high-throughput, low-latency enterprise workloads, crucial for AI training and inference clusters.
• Hardware Accelerators for Reliability: Developing dedicated hardware accelerators and AI/ML-based error correction algorithms to automate operations and enhance data reliability without sacrificing power or latency.
• Next-Gen Interface Integration: Working on controllers that integrate the latest high-speed protocols (PCIe Gen6/7, UCIe, NVMe) to maximize data transfer rates for "Silicon Skyscraper" 3D-IC architectures.