RTL Design Engineer

Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field, with strong experience in digital/RTL design.

• → Design, develop, and maintain high-quality RTL modules using Verilog/SystemVerilog based on architectural and microarchitectural specifications.
• → Work closely with architects to understand requirements and contribute to defining and refining microarchitecture.
• → Develop datapaths, control logic, interfaces, state machines, and other digital blocks for complex SoC designs.
• → Implement and maintain UPF-based low-power intent, including power domains, isolation strategies, level shifters, retention, power states, and related power-management requirements.
• → Translate system-level and block-level specifications into efficient, synthesizable RTL.
• → Analyze design trade-offs involving performance, power, area, and timing (PPAT).
• → Collaborate with verification engineers to develop verification strategies, resolve functional issues, and support simulation and debug activities.
• → Work with physical design teams to address synthesis, timing, power, and implementation-related issues.
• → Perform RTL quality checks, lint analysis, CDC-related reviews, and design reviews as required.
• → Debug RTL and simulation issues and identify root causes across complex design environments.
• → Participate in design reviews and contribute to coding standards, design methodologies, and process improvements.
• → Ensure RTL complies with industry-standard design practices and project specifications.
• → Support integration of IPs and subsystems into larger SoC environments.
• → Review and improve existing RTL for performance, power efficiency, scalability, and maintainability.

• 5–11 years of experience in RTL/Digital Design.
• Strong hands-on expertise in Verilog/SystemVerilog RTL design.
• Strong understanding of microarchitecture and experience converting architectural specifications into RTL implementations.
• Solid experience with UPF (Unified Power Format) and low-power design concepts.
• Good understanding of power domains, isolation cells, level shifters, retention strategies, and power-state management.
• Strong knowledge of digital design fundamentals, including FSMs, datapaths, pipelining, clocking, reset strategies, and synchronous design.
• Experience working on complex SoC, ASIC, CPU, subsystem, or IP-level designs.
• Ability to analyze and resolve functional, performance, power, and timing-related design issues.
• Experience collaborating with cross-functional teams including architecture, verification, DFT, physical design, and STA.

• Experience with low-power SoC design and power-management architectures.
• Familiarity with synthesis, STA, lint, CDC, and RTL quality tools.
• Exposure to semiconductor design flows and ASIC development methodologies.
• Knowledge of clock-domain and reset-domain crossing methodologies.
• Experience with scripting languages such as Python, Perl, or Tcl.
• Familiarity with industry-standard EDA tools and simulation environments.
• Experience with block-level as well as top-level SoC integration.