Design Verification Engineer

You will be responsible for driving silicon quality by preventing bugs from creeping into silicon, and making continuous improvements to address hitherto non-simulatable issues and driving efficiency improvements by adapting and developing methodologies for faster execution.

1.      Verification Planning: Develop detailed, coverage-driven verification plans in close collaboration with System and Design teams. Able to identify the test plan segregation between Analog, digital and analog mixed signal test bench.

2.      Mixed-Signal Modeling: Create behavioral modeling of analog blocks using SV RNM/ Verilog-AMS (wreal, electrical).

3.      System-Level Testing: Identify and develop system-level tests in AMS to ensure bug-free silicon.

4.      Electrical characterization: Identify the Electrical Characterizations scenarios to be verified on SoC top.

5.      Testbench Development: Independently develop testbenches using efficient approaches, develop tests, checkers, and assertions, enhancing them with randomization and coverage.

6.      Methodology Innovation: Drive and implement new, improved design verification methodologies and work with EDA teams to upgrade tools and flows.

7.      Post-Silicon Support: Interact with Test/Validation teams during various post-silicon activities and assist in customer debug and analysis. Address methodology improvements in cases of simulation to silicon correlation gaps. 

8.      Cross-Functional Collaboration: Work closely with Systems engineers, Digital and Analog Designers  to understand the full-chip expectations and test and validation teams during silicon bring-up and debug. 

1.      Education: Bachelor’s or Master’s degree in Electrical or Electronics Engineering.

2.      Mixed-Signal Fundamentals: Strong understanding of analog building blocks, digital design processes, and top-level integration.

3.      Verification Expertise: Proven experience in developing mixed-signal testbenches in SV/UVM from scratch, including the ability to debug and optimize simulation performance and understand necessary trade-offs.

4.      Debug Skills: Strong simulation debug capability with the ability to analyze waveforms and pinpoint issues in schematic simulations or models, including ability to read and interpret analog transistor level schematics and RTL codes. 

5.      Controller Knowledge: Familiarity with analog controllers to develop system-level testbenches and debug complex issues.

1.      Experience: 1–3 years of professional experience in mixed-signal design verification.

2.      Tool Proficiency: Expertise in Cadence Mixed-Signal Design Environment tools (Virtuoso, ADE Assembler, Xcelium, VIVA, and Simvision).

3.      Simulation Mastery: Expertise in Cadence Spectre simulation testbench development, regression flows, and debugging.

4.      HDL Mastery: Advanced proficiency in SystemVerilog, UVM, and Verilog-AMS; experience writing checkers, assertions, and monitors for top-level simulations.

5.      Automation: Proficiency in automation using Python, Perl, Tcl, or Shell scripting.

1.      Drive: A self-driven individual with a thirst for continuous learning.

2.      Communication: Excellent interpersonal and communication skills.

3.      Teamwork: A collaborative attitude with the ability to function effectively both independently and within a team.