Digital and Mixed Signal IC Design/DV Engineer

United States·Tucsonmid

OtherEngineer

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Quick Summary

Key Responsibilities

Design & Implementation: Contribute to the full IC development lifecycle, including RTL design, synthesis, place and route, scan pattern generation, and timing analysis.

Requirements Summary

Atleast 2 years of relevant experience A thorough understanding of digital logic design Familiarity with the Verilog, System Verilog,

Technical Tools

OtherEngineer

Responsibilities

~1 min read

→Atleast 2 years of relevant experience
→A thorough understanding of digital logic design
→Familiarity with the Verilog, System Verilog, VHDL language and simulators
→Ability to solve problems using a systematic approach

Requirements

~1 min read

A good understanding of analog functionality and exposure to analog IC design methods.
Understanding and knowledge of analog and digital design principles, including RTL, FSMs, GLS, timing, synchronization, and power domains, mixed-signal and digital verification flow and analog block modeling.
Experience with timing verification using Gates+SDF, electrical PVT variation, and timing analysis across analog/digital boundaries
Demonstrated strong analytical and problem solving skills
Strong verbal and written communication skills
Ability to work in teams and collaborate effectively with people in different functions
Strong time management skills that enable on-time project delivery
Demonstrated ability to build strong, influential relationships
Ability to work effectively in a fast-paced and rapidly changing environment
Ability to take the initiative and drive for results