10d ago

Senior Digital Design Verification Engineer

India·Bangaloresenior

OtherDesign Verification Engineer

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Quick Summary

Overview

Change the world. Love your job. Texas Instruments is seeking Design Verification Engineer. In this role you will confirm the accuracy of designs for analog and mixed signal electronic parts,

Technical Tools

OtherDesign Verification Engineer

About the Role

~1 min read

Verification Strategy: Drive verification strategy by creating detailed test plans, test cases, and checkers, and developing comprehensive chip-top testbenches.
UVM Architecture: Develop UVM environments from the ground up, including agents, drivers, monitors, and scoreboards.
Full-Cycle Execution: Execute RTL and Gate-Level Simulations (GLS). Run regressions and track functional/code coverage (Block, Expression, Toggle, FSM) to ensure 100% closure. Implement SVAs and coverage models for protocols such as I2C, ASI, SPI, and UART.
Technical Debugging: Resolve complex design and testbench issues using advanced debugging and problem-solving techniques.
Post-Silicon Support: Collaborate with Product and Application Engineering to support ATE functional pattern generation and silicon characterization.
Cross-Functional Collaboration: Partner with Architecture, Design, and Firmware teams to ensure successful product execution.

Requirements

~1 min read

Minimum education Master's or Bachelor's degree in electrical engineering
Minimum of 5 years of experience
Core Competencies: Expertise in SystemVerilog (SV) and UVM methodologies.
Tools: Proficiency in Cadence environments (e.g., Xcelium, vManager, JasperGold).
Communication: Strong interpersonal skills for collaborating with global cross-functional teams and stakeholders.
Formal Verification (FV): Experience with Formal Property Verification (FPV), connectivity checks, and unreachability (UNR) analysis for top-level sign-off.
CDC/RDC: Proficiency in writing and debugging Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) assertions.
Low Power Verification: Experience with UPF (Unified Power Format) and power-aware simulations.

Automation: Proven ability to automate verification flows and repetitive tasks using Python, Perl, or Shell scripting.
Methodology Innovation: Ability to drive improved verification methodologies, collaborate with EDA vendors, and implement AI-driven verification techniques.
Mixed-Signal: Familiarity with AMS (Analog Mixed-Signal) verification environments is a plus.
Technical Leadership: Proactive approach to driving results, managing time effectively, and rapidly mastering new systems and processes.
Collaboration: Strong analytical, interpersonal, and communication skills, with a proven ability to build relationships with global stakeholders and cross-functional teams.