Senior Mixed-Signal Verification Engineer

Arago’s mission is to re-engineer the foundations of computing from first principles.

The explosive growth of AI is pushing the industry to rethink how processors are built. Arago is meeting that challenge with a proprietary technology that fuses optical and CMOS technologies to deliver an order-of-magnitude increase in performance.

Arago is the fastest, and currently the only, company to have built such a processor. It's backed by leading deep-tech investors and some of the most respected figures in semiconductors and computing, including the CEO of Arm, the founder of macOS who worked directly with Steve Jobs at Apple, an Nvidia Fellow, the Head of Optics at Google, and many other industry leaders.

Our work is guided by three clear values: do great things, move with high velocity, and operate as one unit. We work in a demanding environment where constant learning, ownership, and execution are expected, and where exceptional people have the opportunity to do their life’s work.

As Senior Mixed-Signal Verification Engineer you will own the methodology, planning, and execution of mixed-signal verification for digital-to-analog interfaces on Arago's Systems-on-Chip, working across analog, RTL, architecture, and firmware teams to ensure correct integration and drive verification to sign-off.

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  Own the mixed-signal verification methodology and verification plan for digital-to-analog interfaces on Arago SoCs.

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  Build and maintain verification environments at block, subsystem, and SoC level.

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  Develop tests, assertions, checkers, scoreboards, and functional coverage.

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  Verify digital control and configuration of analog/mixed-signal circuitry across normal operation, corner cases, and error conditions.

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  Run regressions, analyze coverage, debug failures, and drive verification to sign-off.

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  Develop or integrate behavioral and real-number models needed for efficient mixed-signal simulation.

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  Work closely with analog, RTL, architecture, firmware, and SoC verification teams to identify and resolve interface issues.

• Strong hands-on experience in ASIC or SoC verification.

• Experience verifying mixed-signal blocks or digital-to-analog and analog-to-digital interfaces.

• Strong SystemVerilog skills and practical experience with UVM or an equivalent verification methodology.

• Experience building verification environments and developing tests, assertions, scoreboards, and functional coverage.

• Good understanding of both digital design fundamentals and basic analog/mixed-signal concepts.

• Strong debugging skills, including the ability to investigate issues spanning RTL, models, clocks, resets, configuration, and analog behavior.

• Experience with scripting and automation, preferably Python, Tcl, shell, or similar.

• Language: English at a proficient level.

• Verification experience with complex high-speed interface IP such as PCIe, DDR/LPDDR, UCIe, SerDes, USB, CXL, or similar PHY-based interfaces.

• Experience verifying interface initialization, link training, calibration, adaptation, clocking, power-state transitions, or other digital/analog control loops.

• Experience with real-number modeling, SystemVerilog RNM, wreal, Verilog-AMS, or equivalent mixed-signal verification techniques.

• Experience developing or integrating behavioral models of analog/PHY components into digital verification environments.

• Experience with SoC-level integration and verification of complex interface IP.

• Experience with low-power verification, power-state management, or UPF.

• Experience driving a complex IP or SoC verification effort through coverage closure and tape-out.