Principal Physical Design Engineer, Methodology

• →Flow & Methodology Ownership
  • →Define, develop, and maintain reusable physical design flows spanning synthesis, place-and-route, extraction, STA, and EMIR
  • →Own the end-to-end RTL-to-GDSII flow infrastructure across multi-vendor toolchains (Cadence Innovus, Tempus, Voltus, Pegasus; Synopsys Fusion Compiler, ICC2, PrimeTime, StarRC)
  • →Evaluate and qualify new tool features, foundry enablement kits, and flow enhancements to continuously improve PPA and schedule predictability
  • →Integrate and maintain DRC/LVS/extraction runsets and ensure consistency with foundry requirements
• →Automation & Scale
  • →Build and enhance automation scripts and infrastructure to manage large-scale multi-corner/multi-mode STA and EMIR runs with efficient partitioning and resource usage
  • →Develop QoR optimization frameworks and tracking methodologies to measure and improve design quality across programs
  • →Partner with IT and compute infrastructure teams to optimize job scheduling, storage, and compute resource utilization
• →Standards, Quality & Enablement
  • →Establish best practices, runset standards, and quality checks that scale across multiple concurrent tapeout programs
  • →Support physical design engineers with flow issues, tool configurations, and methodology guidance
  • →Drive adoption of flow improvements across the team, including training and documentation

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Masters Preferred. 
• 8+ years of experience in physical design methodology, CAD, or flow development for complex SoCs at advanced nodes (7nm and below) 
• Strong knowledge of synthesis, place-and-route, extraction, STA, and equivalence checking flows 
• Experience with both Cadence (Innovus, Tempus, Voltus, Pegasus) and Synopsys (Fusion Compiler, PrimeTime, StarRC, ICC2) toolchains 
• Expert-level scripting ability in Python, Tcl, and/or Perl for flow development and automation 
• Experience building and maintaining multi-corner/multi-mode analysis infrastructure 
• Understanding of foundry design rules, technology files, and enablement kit integration 
• Ability to work independently with strong prioritization and a results-driven mindset 

• Knowledge of agentic AI solutions for EDA automation 
• Experience with CI/CD integration for physical design flows 
• Familiarity with compute farm management and job scheduling optimization 
• Knowledge of advanced packaging or multi-die integration flows 

The base salary range is $185,000 to $240,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives, and benefits.