Senior/Staff System Validation Engineer

Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary System Validation Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters.

The mission of this role is to perform system validation for Astera Lab’s highly advanced devices, that includes defining strategy, develop tools, innovate, be creative to make sure devices are performing as they should in all aspects, logical, performance, durability, stress and more.

You will be part of the site located at Israel (Haifa – Matam), surrounded with highly experienced and professional engineers who will escort, mentor and support you on your journey at Astera Labs Israel.

• Strong academic and technical background in electrical or computer engineering
• 3-5 years experience validating and/or developing complex SoC/silicon products for Networking and/or Server & Storage applications
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and work with minimal guidance and supervision.
• Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind!

• Hands-on, thorough knowledge of high-speed protocols like Ethernet CXL, PCIe, NVMe,.
• Silicon/System bring-up, validation, and debug experience, including customer’s systems.
• A Python coding experience
• Familiarity with validation techniques C, C++
• Experience with lab equipment as protocol analyzers, chambers, in-circuit debuggers, and CPU-based tool suites.
• Familiarity with lab testing automation techniques

• Familiarity with devices trees and related debugging techniques.
• Familiarity with board system design
• C\C++ for embedded FW and device drivers
• Basic understanding of x86/ARM architecture, UEFI/Linux boot sequence
• Familiarity with CXL compliance standards and ability to follow and be involved in compliance consortiums to adapt the tests to be run from X86/ARM based platforms.
• Experience working with DRAM memory vendors on DDR4 or DDR5 to identify issues and working on SoC HW/FW to improve memory calibration and tuning sequences.
• Knowledge of memory subsystem compliance from a data integrity and RAS is a plus.
• Knowledge of schematic capture and PCB layout tools from Cadence, Altium, etc.

Astera Labs is a young light-footed company, allowing our engineers to fully exploit their creativity and innovative thinking to enable you to grow up your engineering capabilities to the maximum!