New
USD $122,785.00 - USD $136,215.00 /Yr

Advanced ASIC FPGA Verification Engineer (Sign-on Bonus Available)

Us-Az-Scottsdalemid
Other
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Quick Summary

Requirements Summary

Candidates must be able to obtain a U.S. Department of Defense TS/SCI security clearance within a reasonable amount of time from date of hire. Applicants selected will be subject to a U.S.

Technical Tools
Other

Requirements

~2 min read

Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 5+ years of job-related experience, or a Master's degree and 3 years of job-related experience.

 

Candidates must be able to obtain a U.S. Department of Defense TS/SCI security clearance within a reasonable amount of time from date of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

 

We encourage you to apply if you have any of these preferred skills or experiences:

  • In-depth experience using RTL simulation tools such as Siemens Mentor Graphics Questa or Modelsim tools or equivalent in a Linux Environment
  • In-depth knowledge of System Verilog object oriented programming and the Universal Verification Methodology (UVM)
  • Understands UVM Testbench Architectures 
  • Comfortable using and developing UVM agents, bus functional models
  • Understands different types of coverage, usage of cover classes, cover points, etc
  • Experience with predictive testbench components, functional coverage and assertions
  • Experience with constrained random testing
  • Experience with the Register Abstraction Layer
  • Familiarity with requirements-based verification, requirement tracing, and developing requirement verification strategies etc
  • Experience with scripting languages such as Linus shell scripts, TCL, Python
  • Familiarity with using Formal Verification tools, code coverage, writing waivers etc
  • Familiarity with the following are also helpful
  • Questa Verification IP (QVIP)
  • Developing UVM testbenches for designs implemented in Xilinx devices with Xilinx IP and SoCs 
  • AXI protocols, PCIe, Space Wire, and Ethernet interfaces 
  • DSP functions and common signal processing components
  • Familiar with debugging FPGA/ASIC hardware and assisting with HW/SW integration
  • Continuous Integration features of GITLab
  • Clear understanding of embedded micro-processing systems, FPGA Design and Verification using VHDL, and digital circuit analysis and design
  • Collaborative, creative thinker with high proficiency in technical problem solving
  • Team player with effective communication and presentation skills
  • Experience designing high speed interfaces and complex memory designs
  • Commitment to ongoing professional development for yourself and others
  • Identifies opportunities to apply AI for continuous improvement and innovation

Responsibilities

~1 min read
  • An exciting career path with opportunities for continuous learning and development.
  • Research oriented work, alongside award winning teams developing practical solutions for our nation’s security
  • Flexible schedules with every other Friday off work, if desired (9/80 schedule)
  • Competitive benefits, including 401k matching, flex time off, paid parental leave, healthcare benefits, health & wellness programs, employee resource and social groups, and more
  • See more at gdmissionsystems.com/careers/why-work-for-us/benefits

Workplace Options:This position is fully remote, on-site or hybrid/flex, as mutually agreed.You will be a part of the Scottsdale, AZ team. Learn more at https://gdmissionsystems.com/about-us/major-locations/scottsdale

Key Words:   Verification, ASIC, FPGA, SystemVerilog, Verilog, Assertions (SVA), OVM, UVM, Digital Signal Processing (DSP), functional coverage, constrained random, formal verification, constrained random testing 

#CJ1

This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.
USD $122,785.00 - USD $136,215.00 /Yr.

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans

Location & Eligibility

Where is the job
Us-Az-Scottsdale
On-site at the office
Who can apply
Same as job location

About this job

Pay per year
$122,785–$136,215 a year
92% above the $67,500 median for Other jobs on Jobera (122,729 salaries).
Posted
Today
Employer
has 67 open jobs on Jobera.

Listing Details

Posted
October 22, 2026
First seen
October 23, 2026
Last seen
October 23, 2026

Posting Health

Days active
0
Repost count
0
Trust Level
68%
Scored at
October 23, 2026

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Advanced ASIC FPGA Verification Engineer (Sign-on Bonus Available)USD $122,785.00 - USD $136,215.00 /Yr