Digital - ASIC Design Automation Engineer

Eliyan is the chiplet interconnect pioneer behind NuLink, the industry's most efficient chiplet-to-chiplet PHY technology. With Series B funding from leading hyperscalers and AI infrastructure providers, we are scaling our digital design organization to support multiple concurrent IP programs across advanced process nodes.

We are seeking a ASIC Design Automation Engineer to take ownership of our digital design flow infrastructure: continuous integration pipelines, automated quality gates, documentation tooling, and AI-augmented review systems. This is an early-career role structured around an 18-24 month methodology and tooling track, with a defined progression into digital design ownership under dedicated senior mentorship. We hire primarily on engineering fundamentals and demonstrated learning ability; prior experience in this specific domain is not a prerequisite.

In this role, you will develop and maintain the infrastructure that enforces design quality prior to tapeout, accelerates cross-functional review cycles through LLM-driven tooling, and maintains alignment between specifications and final RTL across all active projects. MUST BE WILLING TO WORK ONSITE - M-F

• Own and define the front-end release methodology, including release criteria, handoff checkpoints, and cross-team gating procedures
• Build and maintain Jenkins-based CI for Lint, CDC, RDC, and static timing analysis across active design projects, with automated dashboards and per-project triage workflows
• Integrate quality gates into the RTL handoff process: elaboration checks, SDC review, CSR spec consistency, and coding guideline enforcement
• Standardize waiver management workflows across lint and CDC tools; close vendor AE feedback loops

 

• Implement automated spec-to-RTL consistency checking using LLM-driven diff and review pipelines
• Build documentation generation infrastructure (version-controlled, CI-integrated) and prototype LLM-driven RTL review tooling
• Evaluate and integrate new AI/LLM tooling into the design flow; benchmark output quality and establish guardrails for team-wide rollout

• Ramp on CDC fundamentals, shared library design, MCU/SoC integration, and lint methodology under dedicated senior mentorship
• Contribute to RTL development on shared library and CDC-adjacent blocks as readiness builds, with a structured path to digital design ownership over 18-24 months and quarterly readiness reviews

• BS or MS in Computer Engineering, Electrical Engineering, Computer Science, or a related technical field
• Demonstrated ability to acquire new technical domains rapidly, evidenced by coursework, projects, internships, research, or open-source contributions
• Proficiency in Python, Tcl, shell scripting, Git, and Linux; working familiarity with Makefiles and CI/CD systems (Jenkins, GitHub Actions, GitLab CI, or equivalent)
• Foundational understanding of digital logic design, SystemVerilog or other HDLs, and computer architecture
• Strong written and verbal communication, with the ability to produce technical documentation that enables team-wide adoption
• Self-directed problem-solving disposition and comfort operating in a fast-paced, evolving environment
• Authorized to work in the United States; sponsorship may be considered for exceptional candidates

• 3+ years of relevant industry experience
• Hands-on experience with LLM/AI tooling and agent frameworks (Anthropic Claude, OpenAI, or equivalent)
• Familiarity with industry-standard EDA tools (Synopsys VCS, Verdi, PrimeTime, Design Compiler, Fusion Compiler; Cadence Genus; Spyglass; Questa; JasperGold)
• Background in machine learning or data engineering, including production model development or pipeline construction
• Embedded systems or microcontroller firmware experience (ARM Cortex-M class or similar)
• Coursework or project exposure to digital design, SoC, PHY, SerDes, or chiplet interconnect domains
• Open-source contributions to design automation, hardware verification, or developer tooling