Physical Design Engineer
Quick Summary
About Etched Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200.
Deeply understand what is involved in physical design Running PD flows to close blocks, support ASIC infrastructure, automate PD flows,improve CAD infrastructure Collaborate with RTL Designers and provide Physical Design feedback to improve PPA…
Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Etched is looking for exceptional Physical Design engineers to join our team. In this role, you
will own block-level implementation and verification, drive timing closure and PPA optimization, supervise 3rd party design work, and help improve our design flows and iteration speed.
Responsibilities
~1 min read- →
Deeply understand what is involved in physical design
- →
Running PD flows to close blocks, support ASIC infrastructure, automate PD flows,
improve CAD infrastructure - →
Collaborate with RTL Designers and provide Physical Design feedback to improve PPA
- →
Drive dashboards that show the convergence of projects related to PD
- →
Optimize tool flows, working with EDA vendors to incorporate the latest features
- →
Accountable for block level closure
- →
Supervise the outsourcing of physical design to a 3rd party service
5-10+ years of previous experience with PD
Tools, flow, and design methodology from RTL synthesis to GDSII sign-off
Experience with back-end design and timing closure on advanced process nodes (5nm
and below)Experience with Cadence (Innovus, Genus) or Synopsys (ICC2, Fusion Compiler)
automated RTL-to-GDSII flowsExperience with sign-off tools (PrimeTime, Tempus, Voltus, etc.)
Experience with UPF-based low power design methodology, power verification,synthesis, scan insertion/ATPG, formal verification, floorplanning, placement, CTS,
routing, IR drop, and EM/antenna analysisDeeply creative and able to think from first principles
Familiarity with transformer models and machine learning
Ability to program with Python or another scripting language
Familiarity with AI tools for programming/coding
Startup experience or comfort working in fast-paced environments
What We Offer
~1 min readEtched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We have a growing presence in Austin and a core team in San Jose (Santana Row), and we greatly value engineering skills. We do not have strict boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.
Location & Eligibility
Listing Details
- Posted
- April 16, 2026
- First seen
- May 6, 2026
- Last seen
- May 8, 2026
Posting Health
- Days active
- 0
- Repost count
- 0
- Trust Level
- 19%
- Scored at
- May 6, 2026
Signal breakdown
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