RTL Design Engineer

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

As an RTL Engineer at Etched, you will be critical in ensuring that our AI chips operate correctly and efficiently. You will develop and implement design verification strategies for both our existing and upcoming ASIC designs.

In this role, you will work closely with state-of-the-art architectures for machine learning. You do not need to have experience working with these yet, but you will be willing and able to learn quickly. You will work in a fast-paced environment with a high degree of autonomy, and be responsible for a key part of Etched’s success.

• Implement a block to efficiently compute floating point math operators

• Provide feedback to the uArch team to make sure blocks meet timing and area constraints

• At least 5 years of work experience in RTL development.

• Experience with high-speed digital logic.

• Proficiency in standard RTL design and synthesis tools

• Familiarity with verification work and writing test benches

• Are able to learn quickly about transformers and other aspects of modern artificial intelligence

• Willing to start quickly

• Experience with PCIe, Ethernet, or HBM technologies

• Familiarity with modern ML and LLM model architectures.

• Familiarity with numerical representations and functions

• ​Ability to program with Python or another scripting language

We encourage you to apply even if you do not believe you meet every single qualification.

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.