ASIC Engineer

Are you passionate about building advanced semiconductor systems that power next-generation wireless technologies? At Falcomm, we are transforming innovative semiconductor research into real-world products through energy-efficient RF power amplifier and wireless solutions. Our mission is to push the boundaries of performance, efficiency, and integration in modern communication systems.

Falcomm is seeking an ASIC Engineer to support the development of mixed-signal and digital integrated circuits that interface with our RF technologies. This role will contribute to the design, implementation, and verification of ASIC components within larger system-on-chip platforms. The position requires strong collaboration with RFIC, analog, verification, and system engineering teams to deliver high-performance silicon solutions.

• →Design and implement digital and/or mixed-signal ASIC blocks from specification to tapeout
• → Develop RTL (Verilog/SystemVerilog) and/or transistor-level designs depending on focus area
• → Collaborate with RFIC, analog, and system engineers to integrate digital logic within RF and mixed-signal chip architectures.
• → Perform synthesis, timing closure, and power optimization
• → Work with verification engineers to define testbenches and ensure robust design validation
• →Support functional verification and debugging of ASIC components in collaboration with verification teams.
• →Assist with synthesis, timing analysis, and physical implementation activities to ensure design readiness for tape-out.
• →Contribute to silicon bring-up, debugging, and post-silicon validation activities.
• →Document design architecture, implementation details, and verification results.

• Bachelor’s or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.

• 1-3 years of experience developing and implementing in ASIC design.
• Strong experience with RTL design (Verilog/SystemVerilog) and/or analog/mixed-signal IC design
• Solid understanding of digital design fundamentals (timing, clocking, power, etc.)
• Experience with ASIC tool flows (e.g., Synopsys, Cadence, or similar)
• Familiarity with verification methodologies (UVM is a plus)
• Strong problem-solving skills and ability to work across disciplines
• Must be willing to work full-time, onsite, in Atlanta, GA.

• Strong problem-solving skills in complex digital design areas such as clock domain crossing, timing optimization, and low-power design techniques.
• Hands-on experience with industry EDA tools including HDL simulators, linting tools, and FPGA development platforms.
• Proficiency in scripting languages such as Python or TCL to support design automation and verification workflows.