Senior Methodologist for AIML Enhanced Design/Verification

We are seeking a Senior AIML enhanced Design/Verification Methodology Engineer to join our team. In this role, you will be responsible for developing and executing comprehensive verification strategies for complex digital designs using AIML enhanced methodologies. You will architect, build, and maintain AIML enhanced or agentic solutions for design and verification environments with applications to all phases of design and verification closure. You will collaborate closely with design and system engineering teams to ensure silicon quality from RTL to tapeout. This is a high-impact position for someone who thrives on solving intricate design/verification challenges using AIML methodologies.

• →Use both “classical” and Generative-AI methodologies to architect, develop, and maintain agents, skills, and other AI based design and verification infra-structures. The ideal person will have balanced knowledge of chip design and AIML methodologies to contribute meaningfully to the creation of architecture, design, verification, and physical design assets. These includes but not limited to:  
• →Creating UVM-based testbench environments from ground up or enhance the existing ones using AI. Creating verification plans with clear coverage goals and closure criteria. Performing root cause analysis of failures and work with design teams to drive resolution.
• →Automating generation of RTL from spec. 
• →Evaluation of industry tools. 

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science (or equivalent).
• 3 -5 years of direct hands-on experience with AIML methods, concepts and workflows — including experience in creating agents, skills, APIs, model, etc. for Design/Verification problem. 
• 5 - 7 years of experience in production development of RTL design and verification infrastructure.  Strong experience in SystemVerilog for design or verification. 
• Solid understanding of digital design fundamentals (RTL, timing, synthesis constraints).
• Experience with industry-standard simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).
• Effective communication and collaboration skills in cross-functional team settings.

• Master's or Ph.D. in Electrical Engineering or Computer Science.
• Experience with formal verification tools and techniques (e.g., JasperGold, VC Formal) is a plus. Experience with emulation and FPGA prototyping platforms (e.g., Palladium, Protium, Veloce) is also a plus.
• Industry conference/peer reviewed journal publications in the design/verification methodology development and/or AIML.

If you are passionate about verification excellence and want to make a lasting impact on next-generation silicon, we'd love to hear from you. Please submit your resume and a brief summary of your verification experience. We look forward to reviewing your application!

HPE is committed to creating an inclusive and accessible workplace and encourages applications from all qualified individuals, including those with disabilities. If you believe you require accommodation during any stage of the application or interview process, please submit your request by completing our secure form linked here.

Note: This option is reserved for applicants needing assistance/reasonable accommodation related to a disability.

We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.

We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.

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Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html

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