Technical VP - Computing Bus System Research

The Computing Data Application Acceleration Lab aims to create a leading global data analytics platform organized into three specialized teams using innovative programming technologies. This team focuses on full-stack innovations, including software-hardware co-design and optimizing data efficiency at both the storage and runtime layers. This team also develops next-generation GPU architecture for gaming, cloud rendering, VR/AR, and Metaverse applications.

One of the goals of this lab are to enhance algorithm performance and training efficiency across industries, fostering long-term competitiveness.

• Conduct in-depth insight and analysis of industry cutting-edge bus architectures and technologies, develop long-term technology plans and roadmaps, and lead technical decision-making.

• Build competitive bus architectures and interconnection protocols for AI/general computing scenarios, in align with mainstream architectures and protocols in the industry. Drive the continuous evolution of bus technology, ensuring an industry-leading competitive edge of large-scale computing cluster solutions.

• Deeply understand the chip architecture and software framework. Implement system-level innovative solutions centered around bus architecture and protocols. Drive co-innovation across chip design, hardware/software, and solutions to ensure business success.

• Solid foundational knowledge in computer science and computer architecture. In-depth knowledge of bus/network protocols such as PCIe, CXL, and InfiniBand. Familiarity with technologies related to in-order delivery, congestion, retransmission, multipath, flow control, QoS, network measurement, fault tolerance, and reliability. Experience in architecture design and R&D is preferred in scenarios such as high bandwidth, low latency, and homogeneous/heterogeneous computing interconnection. 

• Familiarity with AI large model training, big data, search and push, distributed database, and other application scenarios. Experience in large-scale computing cluster architecture design, hardware-software co-optimization for performance, and relevant implementation outcomes are preferred.

• Experience in leading the planning, architecture design, and implementation of relevant chips or products. 

• Strategic vision and technical leadership, with strong communication skills and good insight.